DS1236A
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When the RC pin is tied to ground, the DS1236A is designed to interface with NMOS processors which
do not have the microamp currents required during a battery backed mode. Grounding the RC pin does,
however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems
incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping
functions be battery backed. When the processor is not battery backed (RC = 0), all signals connected
from the processor to the DS1236A are disconnected from the backup battery supply, or grounded when
system V
CC
decays below V
BAT
. In the NMOS processor system, the principal emphasis is placed on
giving early warnings with NMI , then providing a continuously active RST and RST signal during
power-down while isolating the backup battery from the processor during a loss of V
CC
.
During power-down, NMI will pulse low for a minimum of 200 μs, and then return high. If RC is tied
low (NMOS mode), the voltage on NMI will follow V
CC
until V
CC
supply decays to V
BAT
, at which point
NMI will enter tri-state (see timing diagram). Also, upon V
CC
out of tolerance at V
CCTP
, the RST and
RST outputs are driven active and RST will follow V
CC
as the supply decays. On power-up, RST follows
V
CC
up, RST is held low, and both remain active for t
RST
after valid V
CC
. During a power-up from a V
CC
voltage below V
BAT
, any detected IN pin levels below V
TP
are disabled from reaching the NMI pin until
V
CC
rises to V
CCTP
. As a result, any potential NMI pulse will not be initiated until V
CC
reaches V
CCTP
.
Removal of an active low level on the NMI pin is controlled by either an internal timeout (when the IN
pin is less than V
TP
), or by the subsequent rise of the IN pin above V
TP
. The initiation and removal of the
NMI signal results in an NMI pulse of 0 μs minimum to 500 μs maximum during power-up, depending
on the relative voltage relationship between V
CC
and the IN pin. As an example, when the IN pin is tied to
ground, the internal timeout will result in a pulse of 200 μs minimum to 500 μs maximum. In contrast, if
the IN pin is tied to V
CCO
, NMI will not produce a pulse on power-up.
Connecting the RC pin to a high (V
CCO
) invokes CMOS mode and provides nonvolatile support to both
the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it is
possible to place the microprocessor into a very low-power mode termed the “stop” or “halt” mode. In
this state the CMOS processor requires only microamp currents and is fully capable of being battery
backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM
as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by
any of several different signals. To maintain this low-power state, the DS1236A issues no NMI and/or
reset signals to the processor until it is time to bring the processor back into full operation. To support the
low-power processor battery backed mode (RC = 1), the DS1236A provides a pulsed
NMI for early
power failure warning. Waiting to initiate a Stop mode until after the NMI pin has returned high will
guarantee the processor that no other active NMI or RST/RST will be issued by the DS1236A until one
of two conditions occurs: 1) Voltage on the pin rises above V
TP
, which activates the watchdog, or 2) V
CC
cycles below then above V
BAT
, which also results in an active RST and RST . If V
CC
does not fall below
V
CCTP
, the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises
above V
TP
.
With the RC pin tied to V
CCO
, RST and RST are not forced active as V
CC
collapses to V
CCTP
. The RST is
held at a high level via the external battery as V
CC
falls below battery potential. This mode of operation is
intended for applications in which the processor is made nonvolatile with an external source, and allows
the processor to power down into a Stop mode as signaled from
NMI at an earlier voltage level. The NMI
output pin will pulse low for t
NMI
following a low voltage detect at the IN pin of V
TP
. Following t
NMI
,
however,
NMI will also be held at a high level (V
BAT
) by the battery as V
CC
decays below V
BAT
. On
power-up, RST and RST are held inactive until V
CC
reaches V
BAT
, then RST and RST are driven active
for t
RST
. If the IN pin falls below V
TP
during an active reset, the reset outputs will be forced inactive by
