DS1236A
6 of 20
If the IN pin is connected to V
CCO
, the NMI output will pulse low as V
CC
decays to V
CCTP
in the NMOS
mode (RC=0). In the CMOS mode (RC=V
CCO
) the power-down of V
CC
out of tolerance at V
CCTP
will not
produce a pulse on the
NMI pin. Given that any NMI pulse has been completed by the time V
CC
decays
to V
CCTP
, the NMI pin will remain high. The NMI voltage will follow V
CC
down until V
CC
decays to
V
BAT
. Once V
CC
decays to V
BAT
, the NMI pin will either remain at V
OHL
or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236A provides all of the necessary functions required to battery back a static RAM. First, a
switch is provided to direct SRAM power from the incoming 5-volt supply (V
CC
) or from an external
battery (V
BAT
), whichever is greater. This switched supply (V
CCO
) can also be used to battery back a
CMOS microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output (CEO ) to within 0.3 volts of V
CC
or to within 0.7
volts of V
BAT
. This write protection mechanism occurs as V
CC
falls below V
CCTP
as specified. If CEI is
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high or
the period t
CE
expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of V
CC
-fail detection, CEO will be
unconditionally disabled within t
CF
. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application. The
DS1236A unlike the DS1236 can be operated without a battery. In this method of operation the V
BAT
, pin
1, must be grounded. In general, it would also be expected to have the RC, pin 8, grounded (NMOS
mode) since no battery backup is available.
FRESHNESS SEAL
In order to conserve battery capacity during initial construction of an end system, the DS1236A provides
a freshness seal that electrically disconnects the battery. This means that upon battery attach, the V
CCO
output will remain inactive until V
CC
is applied. This prevents V
CCO
from powering other devices when
the battery is first attached, and V
CC
is not present. Once V
CC
is applied, the freshness seal is broken and
cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236A may not be large enough to support the required load through
V
CCO
with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 8, power to the load is switched from V
CC
to
battery on power-down, and from battery to V
CC
on power-up. The DS1336 is designed to use the PF
output to switch between V
BAT
and V
CC
It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage V
BAT
, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236A supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST,
RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery-operated processor applications.
