XRT85L61 xr
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. 1.0.2
9
1.1.1 64 kHz + 8 kHz Clock Extraction
The input data is shown in Figure 4. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation.
Both the 64 kHz and 8 kHz components are extracted from the composite received signal and presented at the
64 kHz and 8 kHz output pins.
1.1.2 64 kHz + 8 kHz + 400 Hz Clock Extraction
Figure 4 shows the input data for this mode. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar
Violation removed every 400 Hz. The 64 kHz, 8 kHz and 400 Hz components are extracted from the composite
received signal and presented at the RClk, 8 kHz and 400 Hz output pins.
NOTE: The inputs are not aligned with all output signals. The above diagram is used to depict the output activity when the
input signals have errors.
TABLE 8: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT
FREQUENCY (A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
Load Impedance 110 Ω resistive
Transmission Media Symmetric Pair Cable
Pulse Width (FWHM) < 7.8 ± 0.78 µs
Amplitude < 1 V ± 0.1 V
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)
V
V
V
V
RTIP/
RRING
64kHz
Clock
RPOS
RNEG
8kHz Clock
RClk_LCV
8kH_LCV
Missing Pulse Missing Pulse or Wrong Polarity Pulse
Missing Pulse
Missing Pulse
Missing Pulse Not Valid Violation
Not Valid Violation
Missing Pulse or No Violation Bit
If Pulse Missing at RTIP/RRING
out of sync
