xr XRT85L61
REV. 1.0.2 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
14
2.0 AIS DETECTION TIMING
In E1 mode, AIS is set when the received incoming signal has 2 or less Zero’s in a sequence of 512 bits. AIS
will stay “High” for 250 µs and AIS is cleared upon receiving three or more Zero’s in the subsequent 512 bits
(250µs) time-frame.
Figure 9 shows the AIS timing.
In T1 mode, AIS is detected if the received input signal has 4 or less Zero’s in a sequence of 4632 bits (3ms)
and AIS is cleared when 5 or more Zero’s are detected in the subsequent 4632 bits (3 ms) time-frame.
Figure 10 shows the AIS timing for T1 mode.
3.0 LOSS OF SIGNAL
The XRT85L61 Receive Loss of Signal (RLOS) monitoring circuits consist of both analog and digital schemes.
Both E1 and T1 meet G.775 RLOS declare and clear criteria. In E1 and 64kb/s modes, RLOS will be set if the
input pattern exceeds 32 bit consecutive zeros. In T1 mode, RLOS will go "High" if the number of consecutive
zeros exceeds 175.
The XRT85L61 RLOS detection circuit also reports RLOS if the input signal level drops below 220mVp (typical)
and RLOS is cleared when the input signal level returns to more than 380mVp (typical) when the input pattern
meets 12.5% density over a 32 bit period.
FIGURE 9. AIS DETECTION FOR E1 MODE
FIGURE 10. AIS DETECTION FOR T1 MODE
E1
DATA
AIS
250µs250µs
00
000
3 ms 3 ms
T1
DATA
AIS
0000
0 00000
