MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V
DVDDIO
= +5.0V, V
AVDD
= +3.3V, V
DVDD
= +2.5V, V
REFADC
= +3.3V, system clock = 16MHz. T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Capacitance I/O pins three-state 15 pF
PD0._ = 0 880
Maximum Output Impedance
PD0._ = 1 450
SYSTEM CLOCK
System Clock Frequency f
SYSCLK
From any clock source 0 16.67 MHz
SPI INTERFACE TIMING
SPI Master Operating
Frequency
f
MCLK
0.5 x f
SYSCLK
8 MHz
SPI Slave Mode Operating
Frequency
f
SCLK
f
SYSCLK
/8 MHz
SCLK Output Pulse-Width
High/Low
t
MCH
,
t
MCL
t
SYSCLK
- 25
ns
SCLK Input Pulse-Width
High/Low
t
SCH
, t
SCL
t
SYSCLK
ns
MOSI Output Hold Time
After SCLK Sample Edge
t
MOH
t
SYSCLK
- 25
ns
MOSI Output Setup Time to
SCLK Sample Edge
t
MOS
t
SYSCLK
- 25
ns
MISO Input Setup Time to
SCLK Sample Edge
t
MIS
30 ns
MISO Input Hold Time After
SCLK Sample Edge
t
MIH
0ns
SCLK Inactive to MOSI
Inactive
t
MLH
t
SYSCLK
- 25
ns
MOSI Input Setup Time to
SCLK Sample Edge
t
SIS
30 ns
MOSI Input Hold Time After
SCLK Sample Edge
t
SIH
t
SYSCLK
+ 25
ns
MISO Output Valid After
SCLK Shift Edge Transition
t
SOV
3 t
SYSCLK
+ 25
ns
MISO Output Disabled After
SS Edge Rise
t
SLH
2 t
SYSCLK
+ 50
ns
SS Falling Edge to MISO Active t
SOE
2 t
SYSCLK
+ 2.5
ns
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
8 _______________________________________________________________________________________
Note 1: All devices are 100% production tested at T
A
= +25°C and +125°C. Temperature limits to T
A
= -40°C are guaranteed by
design.
Note 2: All analog functions disabled and all digital inputs connected to supply or ground.
Note 3: High-speed/8 mode without CAN; V
DVDD
= +2.5V, CPU and 16-bit timer running at 2MHz from an external, 16MHz crystal
oscillator; all other peripherals disabled; all digital I/Os static at V
DVDDIO
or GNDIO; T
A
= T
MIN
to T
MAX
.
Note 4: High-speed/1 mode with CAN; V
DVDD
= +2.5V, CPU and 16-bit timer running at 16MHz from an external, 16MHz crystal
oscillator; CAN enabled and communicating at 500kbps; all other peripherals disabled, all digital I/Os (except CANTXD
and CANRXD) static at V
DVDDIO
or GNDIO, T
A
= T
MIN
to T
MAX
.
Note 5: Low speed, PMM1 mode without CAN; V
DVDD
= +2.5V, CPU and one timer running from an external, 16MHz crystal oscilla-
tor in PMM1 mode; all other peripherals disabled; all digital I/Os static at V
DVDDIO
or GNDIO, T
A
= T
MIN
to T
MAX
.
Note 6: CAN transmitting at 500kbps; 16-bit timer output switching at 500kHz; all active I/Os are loaded with a 20pF capacitor; all
remaining digital I/Os are static at V
DVDDIO
or GNDIO, T
A
= T
MIN
to T
MAX
.
Note 7: Guaranteed by design and characterization.
Note 8: This is not a static capacitance. It is the capacitance presented to the analog input when the T/H amplifier is in sample mode.
Note 9: The switched capacitor on the REFADC input can disturb the reference voltage. To reduce this disturbance, place a 0.1µF
capacitor from REFADC to AGND as close as possible to REFADC.
Note 10: The digital design is fully static. However, the lower clock limit is set by a clock detect circuit. The MAXQ7670 switches to
the internal RC clock if the external input goes below 166kHz. This clock detect circuit also acts to detect a crystal failure
when a crystal is used.
ELECTRICAL CHARACTERISTICS (continued)
(V
DVDDIO
= +5.0V, V
AVDD
= +3.3V, V
DVDD
= +2.5V, V
REFADC
= +3.3V, system clock = 16MHz. T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SS Falling Edge to First SCLK
Sample Edge
t
SSE
2 t
SYSCLK
+ 5
ns
SCLK Inactive to SS Rising
Edge
t
SD
t
SYSCLK
+ 10
ns
Minimum CS Pulse Width t
SCW
t
SYSCLK
+ 10
ns
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
_______________________________________________________________________________________ 9
MISO
MOSI
SCLK
(CKPOL/CKPHA =
0/1 OR 1/0 MODE)
SCLK
(CKPOL/CKPHA =
0/0 OR 1/1 MODE)
SAMPLE EDGE
SHIFT EDGE
t
MLH
t
MOH
t
MOS
t
MIH
t
MIS
t
MCL
t
MCH
t
MCH
t
MCLK
t
MCL
HIGH IMPEDANCE
Figure 1. SPI Timing Diagram in Master Mode
t
SLH
t
SOV
t
SOE
MISO
MOSI
t
SIS
t
SCH
t
SCL
t
SCL
t
SCW
t
SSE
t
SCH
t
SCLK
t
SIH
t
SD
SAMPLE EDGE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SHIFT EDGE
SCLK
(CKPOL/CKPHA =
0/1 OR 1/0 MODE)
SS
SCLK
(CKPOL/CKPHA =
0/0 OR 1/1 MODE)
Figure 2. SPI Timing Diagram in Slave Mode

MAXQ7670ATL/V+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union