Pump Capacitors
Increasing the pump capacitor value (C4, C6, and C7)
lowers the effective source impedance and increases
the output-current capability. Increasing the capaci-
tance indefinitely has a negligible effect on output cur-
rent capability because the internal switch resistance
and the diode impedance place a lower limit on the
source impedance. A 0.1µF ceramic capacitor works
well in most low-current applications. For the negative
charge pump, the flying capacitor’s voltage rating must
exceed the following:
where n is the stage number in which the flying capaci-
tor appears.
For the positive charge pump, the pump capacitor’s
voltage rating must exceed the following:
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output-voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where C
OUT
_
CP
is the output capacitor of the charge
pump, I
LOAD
_
CP
is the load current of the charge
pump, and V
RIPPLE_CP
is the peak-to-peak value of the
output ripple.
Output-Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from
POUT to GND with the center tap connected to FBP
(Figure 1). Select the lower resistor of divider R5 in the
10kΩ to 30kΩ range. Calculate upper resistor R6 with
the following equation:
where V
FBP
is the positive charge-pump regulator’s
feedback set point.
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R3 in the 20kΩ to 68kΩ range.
Calculate R4 with the following equation:
where V
REF
- V
FBN
is the negative charge-pump regula-
tor’s feedback set point. Note that REF can only source
up to 50µA. Using a resistor less than 20kΩ for R2 results
in higher bias current than REF can supply.
PCB Layout Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of respective high-current loops
by placing step-up regulator’s inductor, diode, and
output capacitors near its input capacitors and its
LX and PGND pins. For the step-up regulator, the
high-current input loop goes from the positive termi-
nal of the input capacitor to the inductor, to the IC’s
LX pins, out of PGND, and to the input capacitor’s
negative terminal. The high-current output loop is
from the positive terminal of the input capacitor to
the inductor, to the output diode (D1), to the posi-
tive terminal of the output capacitors, reconnecting
between the output capacitor and input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in
the high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
• Create a power ground island (PGND) for the step-
up regulator, consisting of the input and output
capacitor grounds and the PGND pin. Connect all
these together with short, wide traces or a small
ground plane. Create an analog ground plane
(AGND) consisting of the AGND pin, all the feed-
back-divider ground connections, the COMP,
ADEL, and GDBL capacitor ground connections,
and the device’s exposed backside pad.
• Place all feedback voltage-divider resistors as
close as possible to their respective feedback pins.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up switch-
ing noise. Care should be taken to avoid running
any feedback trace near LX, DRVN, C1N, C1P,
C2N, or C2P.
