LT4254
14
4254fb
APPLICATIO S I FOR ATIO
WUU
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standard threshold MOSFET can be used. In applications
from 12V to 15V range, a logic level MOSFET must be
used.
In some applications it may be possible for the V
OUT
pin to
ring below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4254 will be more
susceptible to these transients. This is normal and the
LT4254 has been designed to allow for some ringing
below ground. However, if the application is such that
V
OUT
can ring more than 1V below ground, damage may
occur to the LT4254 and an external diode from ground
(anode) to V
OUT
(cathode) will have to be added to the
circuit as shown in Figure 14 (it is critical that the reverse
breakdown voltage of the diode be higher than the highest
expected V
CC
voltage). A capacitor placed from ground to
V
OUT
directly at the LT4254 pins can help reduce the
amount of ringing on V
OUT
but it may not be enough for
some applications.
During a fault condition, the LT4254 pulls down on the
GATE pin with a switch capable of sinking about 55mA.
Once the GATE voltage drops below the output voltage by
a diode forward voltage, the external zener will forward
bias and the output will also be discharged to GND. In
addition to the GATE capacitance, the output capacitance
will be discharged through the LT4254. In applications
that have very large output capacitors, this could cause
damage to the LT4254. Therefore, the maximum output
capacitance that can be used with the LT4254 is 1000µF.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
LT4254 becomes active and pulls down on GATE). This is
due to the drain to gate capacitance forcing current into R7
and C1 when the drain voltage steps up from ground to V
CC
with an extremely fast rise time. To alleviate this situation,
a Schottky diode should be put across R7 with the cathode
connected to C1 as shown in Figure 16.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. The minimum trace width for
1oz copper foil is 0.02" per amp to make sure the trace
stays at a reasonable temperature. 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/
. Small resistances can cause
large errors in high current applications. Noise immunity
will be improved significantly by locating resistor dividers
close to the pins with short V
CC
and GND traces. A 0.1µF
decoupling capacitor from UV to GND is also required.
Figure 15 shows a layout that meets these requirements.
Figure 14. Negative Output Voltage Protection Diode Application
4254 F14
R5
0.033Ω
LT4254
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER
GND
V
CC
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
MRA4003T3
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R9
40.2k
R6
10Ω
R8
140k
V
OUT
R4
27k
C
L
100µF
C2
33nF
C3
0.1µF
C1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
GND
