LTC4222
12
4222fb
When the CONFIG pin is high the two channels work
completely independently and ignore the behavior of the
other channel. This allows for the channels to start up in
sequence by connecting the GPIO (power good) output of
one channel to the UV pin of the other channel.
The two channels share the TIMER and SS (soft-start)
pins that control start-up behavior. If the CONFIG pin is
high and one channel is enabled while the other channel
is starting up, the LTC4222 will wait for the start-up cycle
to end before starting up the second channel to ensure
that it gets a full timer cycle. The exception to this is the
ON pins, which turn on the corresponding channel imme-
diately. When both channels start up simultaneously, the
inrush current for both channels is limited by whichever
FB pin is lowest.
Included in the LTC4222 is a 10-bit A/D signal. The 6-input
multiplexer ahead of the A/D converter allows to select
between the two ADIN pins, the two SOURCE pins and
the two current sense devices.
An I
2
C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the ALERT line is configured as
an interrupt, the host is enabled to respond to faults in
real time. The SDA line is divided into an SDAI (input)
and SDAO (output). This simplifies applications using an
optoisolator driven directly from the SDAO output. The
I
2
C device address is forwarded to the address decoder
from the ADR0, ADR1 and ADR2 pins. These inputs have
three states each that decode into a total of 27 device
addresses.
OPERATION
APPLICATIONS INFORMATION
A typical LTC4222 application is in a high availability system
in which two positive voltage supplies are distributed to
one or more cards. The device measures card voltages
and currents and records past and present fault conditions
for both channels. The system queries each LTC4222 over
the I
2
C periodically and reads status and measurement
information.
A basic LTC4222 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and acts
upon various faults that the LTC4222 detects. External
component selection is discussed in detail in the Design
Example section.
Turn-On Sequence
The power supplies on a board are controlled by using
external N-channel pass transistors (Q1 and Q2) placed
in the power path. Note that resistor R
Sn
provides current
detection. Resistors R1n, R2n and R3n define undervoltage
and overvoltage levels for the two channels. R5n prevents
high frequency oscillations in Qn and R6n. C1n forms an
optional network that may be used to provide an output
dV/dt limited start-up.
Several conditions must be present before the external
MOSFET for a given channel turns on. First the external
supplies, V
DDn
, must exceed their 2.44V undervoltage
lockout levels. Next the internally generated supply, INTV
CC
,
must cross its 2.64V undervoltage threshold. This gener-
ates a 60µs to 120µs power-on-reset pulse. During reset
the fault registers are cleared and the control registers are
set or cleared as described in the register section.
After a power-on-reset pulse, the LTC4222 goes through the
following turn-on sequence for one or both channels. First
the UV and OV comparators indicate that input power is
within the acceptable range, which is indicated by STATUS
bits 0 to 1 in Table 5. Second, the EN pin is externally pulled
low. Finally, all of these conditions must be satisfied for
the duration of 100ms to ensure that any contact bounce
during insertion has ended. Additionally, if the CONFIG pin
is low all initial conditions for both channels must be met
before the pair are allowed to turn on together.
When these initial conditions are satisfied, the ON pin
is checked and its state written to bit 3 in the CONTROL
register (Table 3). If it is high, the external MOSFET is
turned on. If the ON pin is low, the external MOSFET is
turned on when the ON pin is brought high or if a serial bus
turn-on command is sent by setting CONTROL bit 3. If the
CONFIG pin is low, either both ON pins must be high or
both CONTROL registers third bits must be set in order for
the external MOSFETs to be turned on
simultaneously.
