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LTC4222CUH#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC4222
22
4222fb
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
a7:a0 11
R
0
4222 F11
A A
P
S ADDRESS
a7:a0 a7:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
b7:b00
W
0 0
4222 F10
A
0
A
b7:b0
DATA
A A P
Figure 10. LTC4222 Serial Bus SDA Read Word Protocol
Figure 11. LTC4222 Serial Bus SDA Alert Response Protocol
APPLICATIONS INFORMATION
same seven bit address with the R/W bit now set to one.
The LTC4222 acknowledges and send the contents of the
requested register. The transmission is ended when the
master sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4222 repeats the requested register as
the second data byte.
Alert Response Protocol
When any of the fault bits in the FAULT register are set,
an optional bus alert is generated if the appropriate bit in
the ALERT register is also set. If an alert is enabled, the
corresponding fault causes the ALERT pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4222 responds with its address on the
SDA line and then release ALERT as shown in Figure 11.
The ALERT line is also released if the device is addressed
by the bus master. The ALERT signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
LTC4222
23
4222fb
APPLICATIONS INFORMATION
Table 1. LTC4222 I
2
C Device Addressing
DESCRIPTION
DEVICE
ADDRESS DEVICE ADDRESS
LTC4222
ADDRESS PINS
h 7 6 5 4 3 2 1 0 ADR2 ADR1 ADR0
Mass Write C6 1 1 0 0 0 1 1 0 X X X
Alert Response 19 0 0 0 1 1 0 0 1 X X X
0 88 1 0 0 0 1 0 0 X L NC L
1 8A 1 0 0 0 1 0 1 X L H NC
2 8C 1 0 0 0 1 1 0 X L NC NC
3 8E 1 0 0 0 1 1 1 X L NC H
4 98 1 0 0 1 1 0 0 X L L L
5 9A 1 0 0 1 1 0 1 X L H H
6 9C 1 0 0 1 1
1 0 X L L NC
7 9E 1 0 0 1 1 1 1 X L L H
8 A8 1 0 1 0 1 0 0 X NC NC L
9 AA 1 0 1 0 1 0 1 X NC H NC
10 AC 1 0 1 0 1 1 0 X NC NC NC
11 AE 1 0 1 0 1 1 1 X NC NC H
12 B8 1 0 1 1 1 0 0 X NC L L
13 BA 1 0 1 1 1 0 1 X NC H H
14 BC 1 0 1 1 1 1 0 X NC L NC
15 BE 1 0 1 1 1 1 1 X NC L H
16 C8 1 1 0 0 1 0 0 X H
NC L
17 CA 1 1 0 0 1 0 1 X H H NC
18 CC 1 1 0 0 1 1 0 X H NC NC
19 CE 1 1 0 0 1 1 1 X H NC H
20 D8 1 1 0 1 1 0 0 X H L L
21 DA 1 1 0 1 1 0 1 X H H H
22 DC 1 1 0 1 1 1 0 X H L NC
23 DE 1 1 0 1 1 1 1 X H L H
24 E8 1 1 1 0 1 0 0 X L H L
25 EA 1 1 1 0 1 0 1 X NC H L
26 EC 1 1 1 0 1 1 0 X H H L
LTC4222
24
4222fb
APPLICATIONS INFORMATION
Table 2. LTC4222 Register Addresses and Contents
REGISTER ADDRESS
REGISTER NAME DESCRIPTIONDecimal Hex
208 D0h Control1 (A1) Sets Behavior for Channel 1
209 D1h Alert1 (B1) Selects Which Channel 1 Faults Generate Alerts
210 D2h Status1 (C1) Displays the Status of Channel 1
211 D3h Fault1 (D1) Fault Log for Channel 1
212 D4h Control2 (A2) Sets Behavior for Channel 2
213 D5h Alert2 (B2) Selects which Channel 2 Faults Generate Alerts
214 D6h Status2 (C2) Displays the Status of Channel 2
215 D7h Fault2 (D2) Fault Log for Channel 2
216 D8h SOURCE1 MSB ADC SOURCE1 MSB data
217 D9h SOURCE1 LSB ADC SOURCE1 LSB data
218 DAh SOURCE2 MSB ADC SOURCE2 MSB data
219 DBh SOURCE2 LSB ADC SOURCE2 LSB data
220 DCh ADIN1 MSB ADC ADIN1 MSB
221 DDh ADIN1 LSB ADC ADIN1 LSB
222 DEh ADIN2 MSB ADC ADIN2 MSB
223 DFh ADIN2 LSB ADC ADIN2 LSB
224 E0h SENSE1 MSB ADC SENSE1 MSB
225 E1h SENSE1 LSB ADC SENSE1 LSB
226 E2h SENSE2 MSB ADC SENSE2 MSB
227 E3h SENSE2 LSB ADC SENSE2 LSB
228 E4h ADC CONTROL Configures Behavior of the ADC
+ Set bit ADC_CONTROL(0) before writing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

LTC4222CUH#PBF

Mfr. #:
Buy LTC4222CUH#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Dual Hot Swap Controller w/ADC and I2C
Lifecycle:
New from this manufacturer.
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