MAX15020ATP+ Datasheet MAX15020ATP+T, MAX15020ATP+ | P13-P15

MAX15020

2A, 40V Step-Down DC-DC Converter with

Dynamic Output-Voltage Programming

______________________________________________________________________________________ 13

Input Capacitor Selection

The discontinuous input current of the buck converter

causes large input ripple currents and therefore the

input capacitor must be carefully chosen to keep the

input-voltage ripple within design requirements. The

input-voltage ripple is comprised of ΔV

(caused by the

capacitor discharge) and ΔV

ESR

(caused by the ESR

(equivalent series resistance) of the input capacitor).

The total voltage ripple is the sum of ΔV

and ΔV

ESR

Calculate the input capacitance and ESR required for a

specified ripple using the following equations:

where:

OUT_MAX

is the maximum output current, D is the duty

cycle, and f

is the switching frequency.

The MAX15020 includes internal and external UVLO

hysteresis and soft-start to avoid possible unintentional

chattering during turn-on. However, use a bulk capaci-

tor if the input source impedance is high. Use enough

input capacitance at lower input voltages to avoid pos-

sible undershoot below the UVLO threshold during

transient loading.

Output Capacitor Selection

The allowable output-voltage ripple and the maximum

deviation of the output voltage during load steps deter-

mine the output capacitance and its ESR. The output

ripple is mainly composed of ΔV

(caused by the

capacitor discharge) and ΔV

ESR

(caused by the volt-

age drop across the ESR of the output capacitor). The

equations for calculating the peak-to-peak output volt-

age ripple are:

Normally, a good approximation of the output-voltage

ripple is ΔV

RIPPLE

≈ ΔV

ESR

+ ΔV

. If using ceramic

capacitors, assume the contribution to the output-volt-

age ripple from ESR and the capacitor discharge to be

equal to 20% and 80%, respectively. ΔI

is the peak-to-

peak inductor current (see the

Input Capacitor

Selection

section) and f

is the converter’s switching

frequency.

The allowable deviation of the output voltage during

fast load transients also determines the output capaci-

tance, its ESR, and its equivalent series inductance

(ESL). The output capacitor supplies the load current

during a load step until the controller responds with a

greater duty cycle. The response time (t

RESPONSE

)

depends on the closed-loop bandwidth of the converter

(see the

Compensation Design

section). The resistive

drop across the output capacitor’s ESR, the drop

across the capacitor’s ESL (ΔV

ESL

), and the capacitor

discharge cause a voltage droop during the load step.

Use a combination of low-ESR tantalum/aluminum elec-

trolytic and ceramic capacitors for better transient load

and voltage ripple performance. Surface-mount capaci-

tors and capacitors in parallel help reduce the ESL.

Keep the maximum output-voltage deviations below the

tolerable limits of the electronics powered. Use the fol-

lowing equations to calculate the required ESR, ESL,

and capacitance value during a load step:

where I

STEP

is the load step, t

STEP

is the rise time of the

load step, and t

RESPONSE

is the response time of the

controller.

ESR

ESL

ESR

STEP

OUT

STEP RESPONSE

SSL STEP

STEP

ΔΔ

V ESR I

OUT SW

ESR L

××

=×

ΔI

VV V

Vf L

IN OUT OUT

IN SW

OUT

××

−()

ESR

OUT MAX

⎛

⎝

⎜

⎞

⎠

⎟

(

11−

QSW

)

MAX15020

2A, 40V Step-Down DC-DC Converter with

Dynamic Output-Voltage Programming

14 ______________________________________________________________________________________

Compensation Design

The MAX15020 uses a voltage-mode control scheme

that regulates the output voltage by comparing the

error-amplifier output (COMP) with an internal ramp to

produce the required duty cycle. The output lowpass

LC filter creates a double pole at the resonant frequen-

cy, which has a gain drop of -40dB/decade. The error

amplifier must compensate for this gain drop and

phase shift to achieve a stable closed-loop system.

The basic regulator loop consists of a power modulator,

an output feedback divider, and a voltage error amplifi-

er. The power modulator has a DC gain set by V

RAMP

, with a double pole and a single zero set by the

output inductance (L), the output capacitance (C

OUT

)

(C6 in the Figure 2) and its ESR. The power modulator

incorporates a voltage feed-forward feature, which auto-

matically adjusts for variations in the input voltage

resulting in a DC gain of 9. The following equations

define the power modulator:

The switching frequency is internally set at 300kHz or

500kHz, or can vary from 100kHz to 500kHz when driven

with an external SYNC signal. The crossover frequency

), which is the frequency when the closed-loop gain is

equal to unity, should be set as f

/ 2π or lower.

The error amplifier must provide a gain and phase

bump to compensate for the rapid gain and phase loss

from the LC double pole. This is accomplished by utiliz-

ing a Type 3 compensator that introduces two zeros

and three poles into the control loop. The error amplifier

has a low-frequency pole (f

) near the origin.

In reference to Figures 3 and 4, the two zeros are at:

And the higher frequency poles are at:

Compensation When f

< f

ESR

Figure 3 shows the error-amplifier feedback as well as

its gain response for circuits that use low-ESR output

capacitors (ceramic). In this case f

ZESR

occurs after f

is set to 0.8 x f

LC(MOD)

and f

is set to f

to com-

pensate for the gain and phase loss due to the double

pole. Choose the inductor (L) and output capacitor

OUT

) as described in the

Inductor Selection

and

Output Capacitor Selection

sections.

Choose a value for the feedback resistor R9 in Figure 3

(values between 1kΩ and 10kΩ are adequate).

C12 is then calculated as:

occurs between f

and f

. The error-amplifier gain

) at f

is due primarily to C11 and R9.

Therefore, G

EA(fC)

= 2π x f

x C11 x R9 and the modu-

lator gain at f

is:

Since G

EA(fC)

x G

MOD(fC)

= 1, C11 is calculated by:

is set at 1/2 the switching frequency (f

). R6 is

then calculated by:

Since R7 >> R6, R7 + R6 can be approximated as R7.

R7 is then calculated as:

is set at 5 x f

. Therefore, C13 is calculated as:

CRf

2129 1

×××

−π

211

××π

21105

×××π .

fLC

COUT

MOD DC

×× ×

()

LC f

MOD fC

MOD DC

OUT C

()

×× ×2

208 9

×××π .

and f

PP23

2611

12 13

12 1

××

⎛

⎝

⎜

⎞

⎠

⎟

and f

RR C

ZZ12

2912

26711

××

×+×ππ()

MOD DC

RAMP

ESR

OUT

()

××

EESR

MAX15020

2A, 40V Step-Down DC-DC Converter with

Dynamic Output-Voltage Programming

______________________________________________________________________________________ 15

Compensation when f

> f

ZESR

For larger ESR capacitors such as tantalum and alu-

minum electrolytics, f

ZESR

can occur before f

. If f

ZESR

< f

, then f

occurs between f

and f

. f

and f

remain the same as before, however, f

is now set

equal to f

ZESR

. The output capacitor’s ESR zero fre-

quency is higher than f

but lower than the closed-

loop crossover frequency. The equations that define

the error amplifier’s poles and zeros (f

, f

and f

) are the same as before. However, f

is now

lower than the closed-loop crossover frequency. Figure

4 shows the error-amplifier feedback as well as its gain

response for circuits that use higher-ESR output capac-

itors (tantalum or aluminum electrolytic).

Pick a value for the feedback resistor R9 in Figure 4

(values between 1kΩ and 10kΩ are adequate).

C12 is then calculated as:

The error-amplifier gain between f

and f

is approxi-

mately equal to R9 / R6 (given that R6 << R7). R6 can

then be calculated as:

C11 is then calculated as:

Since R7 >> R6, R7 + R6 can be approximated as R7.

R7 is then calculated as:

is set at 5 x f

. Therefore, C13 is calculated as:

Based on the calculations above, the following com-

pensation values are recommended when the switch-

ing frequency of DC-DC converter ranges from 100kHz

to 500kHz. (Note: The compensation parameters in

Figure 2 are strongly recommended if the switching

frequency is from 300kHz to 500kHz.)

CRf

2129 1

×××

−π

211

××π

C ESR

OUT

910

××

208 9

×××π .

C12

CLOSED-LOOP

GAIN

FREQUENCY (Hz)

ERROR-

AMPLIFIER

GAIN

(dB)

C13

C11

OUT

COMP

ERROR

AMPLIFIER

Figure 3. Error-Amplifier Compensation Circuit (Closed-Loop

and Error-Amplifier Gain Plot) for Ceramic Capacitors

C12

CLOSED-LOOP

GAIN

ERROR-

AMPLIFIER

GAIN

C13

C11

OUT

COMP

ERROR

AMPLIFIER

FREQUENCY (Hz)

GAIN

(dB)

Figure 4. Error-Amplifier Compensation Circuit (Closed-Loop

and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX15020ATP+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Switching Voltage Regulators 2A 40V Step-Down w/Dynamic Output-V

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MAX15020ATP+

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