NXP Semiconductors
TEA1993TS
GreenChip synchronous rectifier controller
TEA1993TS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1.1 — 14 September 2016
4 / 20
7 Pinning information
7.1 Pinning
IC
CAP DRAIN
GND
XV GATE
aaa-021171
1
2
3
6
SOURCE
5
4
Figure 2. TEA1993TS pin configuration (SOT457)
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CAP 1 capacitor input for internal supply voltage
GND 2 ground
XV 3 external supply input
GATE 4 gate driver output for SR MOSFET
SOURCE 5 source sense input of SR MOSFET
DRAIN 6 drain sense input of SR MOSFET
NXP Semiconductors
TEA1993TS
GreenChip synchronous rectifier controller
TEA1993TS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1.1 — 14 September 2016
5 / 20
8 Functional description
8.1 Introduction
The TEA1993TS is a controller IC for Synchronous Rectification (SR) in flyback
applications. It can drive the external synchronous rectifier MOSFET for the rectification
of the voltage on the secondary winding of the transformer. Figure 3 shows a typical
configuration.
DRIVER
PRIMARY
CONTROLLER
SECONDARY
CONTROLLER
S1
CAP
VCC
OPTO
GND
GATE
DRAIN
XV
GND
SOURCE
TEA1993
ISENSE
AUX
VCC
HV
CTRL
GND
PROTECT
8
6
2
7
3
5
4
1
aaa-021177
SR low side
Figure 3. TEA1993TS configuration with low-side rectification
8.2 Start-up and UnderVoltage LockOut (UVLO; CAP and XV pins)
The capacitor on the CAP pin supplies the TEA1993TS. It is charged via the DRAIN
pin when the XV voltage is < 4.7 V. The charge current (I
ch(CAP)
) charges the capacitor
to 4 V. When this voltage is reached, it stops charging. If the external voltage exceeds
4.7 V, the XV pin increases the capacitor voltage via an integrated diode. The increase of
the capacitor voltage gives a higher gate driver voltage (V
G(max)
).
When the voltage on the CAP pin exceeds V
start(CAP)
(3.7 V typical), the IC leaves the
UVLO state and activates the synchronous rectifier circuitry. When the voltage drops
to below 3.6 V (typical), the UVLO state is reentered and the SR MOSFET gate driver
output is actively kept low.
8.3 Drain sense (DRAIN pin)
The drain sense pin is an input pin capable of handling input voltages up to 120 V. At
a positive drain sense voltage, the gate driver is in off-mode with the gate driver pulled
down (pin GATE). At a negative drain sense voltage, the IC enables the Synchronous
Rectification (SR) by sensing the drain source differential voltage.
NXP Semiconductors
TEA1993TS
GreenChip synchronous rectifier controller
TEA1993TS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1.1 — 14 September 2016
6 / 20
8.4 Synchronous rectification (DRAIN and SOURCE pins)
The IC senses the voltage difference between the drain sense (DRAIN pin) and the
source sense (SOURCE pin) connections. This drain source differential voltage of the SR
MOSFET is used to drive the gate of the SR MOSFET.
In the regulation phase, the IC regulates the difference between the drain and the source
sense inputs to an absolute level of 37 mV. When the absolute difference exceeds 37 mV
(V
reg(drv)
), the gate driver output increases the gate voltage of the external SR MOSFET
until the 37 mV level is reached. The SR MOSFET does not switch off at low current. To
avoid that the device switches off because of ringing, a minimum on-time of 1.5 μs (t
tact(sr)
(min)
) is integrated.
When the absolute difference is < 30 mV, the gate driver output decreases the gate
voltage of the external SR MOSFET. The voltage waveform on the SR MOSFET gate
follows the waveform of the current through the SR MOSFET. When the current through
the SR MOSFET reaches zero, the SR MOSFET is quickly switched off.
After SR MOSFET switch-off, the drain voltage increases. When the drain voltage
exceeds 300 mV, a low ohmic gate pull-down of 7 Ω keeps the gate of the SR MOSFET
switched off.
8.5 Gate driver (GATE pin)
The gate driver circuit charges the gate of the external SR MOSFET during the rising part
of the current. The driver circuit discharges the gate during the falling part of the current.
The gate driver has a source capability of typically 0.50 A and a sink capability of typically
0.65 A, allowing fast turn-on and fast turn-off of the external SR MOSFET.
The maximum output voltage of the driver is limited to 12 V. This high output voltage
drives all MOSFET brands to the minimum on-state resistance. In applications where the
IC is supplied with 5 V, the maximum output voltage of the driver is 4.2 V and logic level
SR MOSFETs can be used (see Figure 3).
The IC is self-supplying in applications with high-side rectification or in battery charging
applications with an output voltage below 4.7 V. When the XV pin is connected to ground
for driving standard SR MOSFETs, the driver is regulated to 9 V. When the XV pin is
connected to the converter output for driving logic-level SR MOSFETs, the driver is
regulated to 4 V if the output voltage is below 4.7 V.

TEA1993TS/1X

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Power Management Specialized - PMIC GreenChip synchronous rectifier controller
Lifecycle:
New from this manufacturer.
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