© 2001 Fairchild Semiconductor Corporation DS500102 www.fairchildsemi.com
March 2001
Revised March 2001
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver
74LVTH16835
Low Voltage 18-Bit Universal Bus Driver
with Bushold and 3-STATE Outputs
General Description
The LVTH16835 is an 18-bit universal bus driver that com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE
), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (A
n
) to Outputs (Y
n
) on
a Positive Edge Transition of the Clock. When OE
is LOW,
the output data is enabled. When OE
is HIGH the output
port is in a high impedance state.
The LVTH16835 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The bus driver is designed for low voltage (3.3V) V
CC
appli-
cations, but with the capability to provide a TTL interface to
a 5V environment. The LVTH16835 is fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power up/down high impedance provides glitch-free bus
loading
■ Outputs source/sink
−32 mA/+64 mA
■ ESD Performance:
Human-Body Model
> 2000V
Machine Model
> 200V
Charged-Device Model
> 1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74LVTH16835MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide