CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 4 of 24
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
I/O
10L
I/O
11L
I/O
15L
V
CC
GND
I/O
1R
I/O
2R
V
CC
9091
A
3L
M/S
BUSY
R
I/O
14L
GND
I/O
12L
I/O
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
I/O
0R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
Œ
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C024E/CY7C025E
R/W
L
[4]
[5]
Notes
4. A
12L
on the CY7C025E/CY7C0251E.
5. A
12R
on the CY7C025E/CY7C0251E.
CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 5 of 24
Figure 2. 100-pin TQFP pinout (Top View)
Top View
100-Pin TQFP
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
I/O
11L
I/O
12L
I/O
16L
V
CC
GND
I/O
1R
I/O
2R
V
CC
9091
A
3L
M/S
BUSY
R
I/O
15L
GND
I/O
13L
I/O
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48 49 50
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
10L
GND
I/O
1L
I/O
0L
OE
L
SEM
L
V
CC
CE
L
UB
L
LB
L
NC
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
I/O
0R
I/O
7R
I/O
16R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
NC
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
CY7C0251E
I/O
8L
I/O
17L
I/O
8R
I/O
17R
R/W
L
[7]
[6]
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip enable
R/W
L
R/W
R
Read/write enable
OE
L
OE
R
Output enable
A
0L
–A
11/12L
A
0R
–A
11/12R
Address
I/O
0L
–I/O
15/17L
I/O
0R
–I/O
15/17R
Data bus input/output
SEM
L
SEM
R
Semaphore enable
UB
L
UB
R
Upper byte select
LB
L
LB
R
Lower byte select
INT
L
INT
R
Interrupt flag
BUSY
L
[8]
BUSY
R
[8]
Busy flag
M/S
Master or slave select
V
CC
Power
GND Ground
Notes
6. A
12L
on the CY7C025E/CY7C0251E.
7. A
12R
on the CY7C025E/CY7C0251E.
8. BUSY
is an output in master mode and an input in slave mode.
CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 6 of 24
Architecture
The CY7C024E and CY7C025E/CY7C0251E consist of an array
of 4 K words of 16 bits each and 8 K words of 16/18 bits each of
dual-port RAM cells, I/O and address lines, and control signals
(CE
, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT
) pins can be used for
port-to-port communication. Two semaphore (SEM
) control pins
are used for allocating shared resources. With the M/S
pin, the
CY7C024E and CY7C025E/CY7C0251E can function as a
master (BUSY
pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024E and CY7C025E/CY7C0251E have an
automatic power-down feature controlled by CE. Each port is
provided with its own output enable control (OE
), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W
to guarantee a valid write. A write operation is controlled
by either the R/W
pin (see Figure 7) or the CE pin (see Figure 8).
Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
DDD
after
the data is presented on the other port.
Table 1. Non-Contending Read/Write
Inputs Outputs
Operation
CE R/W OE UB LB SEM I/O
0
I/O
7
[9]
I/O
8
I/O
15
[10]
H X X X X H High Z High Z Deselected: power-down
X X X H H H High Z High Z Deselected: power-down
L L X L H H High Z Data in Write to upper byte only
L L X H L H Data in High Z Write to lower byte only
L L X L L H Data in Data in Write to both bytes
L H L L H H High Z Data out Read upper byte only
L H L H L H Data out High Z Read lower byte only
L H L L L H Data out Data out Read both bytes
X X H X X X High Z High Z Outputs disabled
H H L X X L Data out Data out Read data in semaphore flag
X H L H H L Data out Data out Read data in semaphore flag
H X X X L Data in Data in Write D
IN0
into semaphore flag
X X H H L Data in Data in Write D
IN0
into semaphore flag
L X X L X L Not allowed
L X X X L L Not allowed
Notes
9. I/O
0
–I/O
8
on the CY7C0251E.
10. I/O
9
–I/O
17
on the CY7C0251E.

CY7C025E-25AXC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 128Kb 25ns 8K x 16 Dual Port SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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