Lineage Power 8
Data Sheet
March 28, 2008
3.0 Vdc - 5.5 Vdc Input, 0.9 Vdc - 3.3 Vdc Output, 10 A
Austin Lynx
TM
SMT Non-Isolated dc-dc Power Modules:
Test Configurations
Note: Measure input reflected ripple current with a simulated source
inductance (L
TEST) of 1µH. Capacitor CS offsets possible bat-
tery impedance. Measure current as shown above.
Figure 15. Input Reflected Ripple Current Test Setup.
Note: Scope measurements should be made using a BNC socket,
with a 10 µF tantalum capacitor and a 1 µF ceramic capcitor.
Position the load between 51 mm and 76 mm (2 in and 3 in)
from the module
Figure 16. Peak-to-Peak Output Ripple Measurement
Test Setup.
Note: All voltage measurements to be taken at the module termi-
nals, as shown above. If sockets are used then Kelvin con-
nections are required at the module terminals to avoid
measurement
errors due to socket contact resistance.
Figure 17. Output Voltage and Efficiency Test Setup.
Design Considerations
Input Source Impedance
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the module.
18 shows the input ripple voltage (mVp-p) for various output
models using a 150 µF low ESR polymer capacitor (Pana-
sonic p/n: EEFUE0J151R, Sanyo p/n: 6TPE150M) in parallel
with 47 µF ceramic capacitor (Panasonic p/n: ECJ-
5YB0J476M,
Taiyo Yuden p/n: CEJMK432BJ476MMT). 19 depicts much
lower input voltage ripple when input capacitance is
increased to 450 µF (3 x 150 µF) polymer capacitors in par-
allel with 94 µF (2 x 47 µF) ceramic capacitor.
The input capacitance should be able to handle an AC ripple
current of at least:
Figure 18. Input Voltage Ripple for Various
Output Models, IO = 10 A
(CIN = 150 µF polymer // 47 µF ceramic).
Figure 19. Input Voltage Ripple for Various
Output Models, IO = 10 A (CIN = 3x150 µF
polymer // 2x47 µF ceramic).
BATTERY
L
1 µH
C
S 220 μF
ESR < 0.1 Ω
@ 20 °C, 100 kHz
V
I (+)
V
I (–)
2 x 100µF
Tantalum
VO
GND
RESISTIVE
LOAD
SCOPE
10 µF
COPPER STRIP
TANTALUM
1µF
CERAMIC
VI VO
II
IO
SUPPLY
ONTACT RESISTANCE
CONTACT AND
DISTRIBUTION LOSSES
LOAD
GND
η
V
O(+)
V
O(-)
–[]I
O
×
V
I(+)
V
I(-)
–[]I
I
×
------------------------------------------------
⎝⎠
⎛⎞
100×=
I
rms
I
out
V
out
V
in
-----------
1
V
out
V
in
-----------
–= A
rms
0
50
100
150
200
0.5 1 1.5 2 2.5 3
V
I
= 5 V
V
I
= 3.3 V
O
INPUT VOLTAGE NOISE (mV p-p)
0
25
50
75
100
0.5 1 1.5 2 2.5 3
VI = 5 V
V
I = 3.3 V
O
(Vdc)
INPUT VOLTAGE NOISE (mV p-p)
