DS1742-100IND+ Datasheet DS1742W-150+, DS1742-100, DS1742-100IND+ | P1-P3

DS1742

Y2KC Nonvolatile Timekeeping

RAM

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FEATURES PIN CONFIGURATION

 Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit and

Lithium Energy Source

1 of 16 REV: 102808



Clock Registers are Accessed Identically to

the Static RAM; These Registers are

Resident in the Eight Top RAM Locations

 Century Byte Register

 Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

 BCD Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with

Automatic Leap Year Compensation Valid

Up to the year 2100

 Battery Voltage Level Indicator Flag

 Power-Fail Write Protection Allows for ±10%

V

CC

Power Supply Tolerance

 Lithium Energy Source is Electrically

Disconnected to Retain Freshness until

Power is Applied for the First Time

 Standard JEDEC Bytewide 2k x 8 Static

RAM Pinout

 Quartz Accuracy ±1 Minute a Month at

+25°C, Factory Calibrated

 Underwriters Laboratories (UL®)

Recognized

ORDERING INFORMATION

PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK**

DS1742-85

5.0 0°C to +70°C

24 EDIP (0.740a) DS1742-85

DS1742-85+

5.0 0°C to +70°C

24 EDIP (0.740a) DS1742-85+

DS1742-100

5.0 0°C to +70°C

24 EDIP (0.740a) DS1742-100

DS1742-100+

5.0 0°C to +70°C

24 EDIP (0.740a) DS1742-100+

DS1742-100IND

5.0 -40°C to +85°C

24 EDIP (0.740a) DS1742-100IND

DS1742-100IND+

5.0 -40°C to +85°C

24 EDIP (0.740a) DS1742-100IND+

DS1742W-120

3.3 0°C to +70°C

24 EDIP (0.740a) DS1742W-120

DS1742W-120+

3.3 0°C to +70°C

24 EDIP (0.740a) DS1742W-120+

DS1742W-150

3.3 0°C to +70°C

24 EDIP (0.740a) DS1742W-150

DS1742W-150+

3.3 0°C to +70°C

24 EDIP (0.740a) DS1742W-150+

+Denotes a lead(Pb)-free/RoHS-compliant device.

**The top mark will include a “+” on lead(Pb)-free devices.

UL is a registered trademark of Underwriters Laboratories, Inc.

V

CC

A8

A9

WE

OE

A10

CE

DQ7

DQ6

DQ5

DQ4

DQ3

1

2

3

4

5

6

7

8

9

10

11

GND

12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

24

23

22

21

20

19

18

17

16

15

14

13

DS1742

TOP VIEW

ENCAPSULATED DIP

DS1742

2 of 16

PIN DESCRIPTION

PIN NAME FUNCTION

1 A7

2 A6

3 A5

4 A4

5 A3

6 A2

7 A1

8 A0

19 A10

22 A9

23 A8

Address Input

9 DQ0

10 DQ1

11 DQ2

13 DQ3

14 DQ4

15 DQ5

16 DQ6

17 DQ7

Data Input/Output

12 GND Ground

18 CE Active-Low Chip-Enable Input

20 OE Active-Low Output-Enable Input

21 WE Active-Low Write-Enable Input

24 V

CC

Power-Supply Input

DESCRIPTION

The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and

2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished

with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in

the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day,

hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month

and leap year are made automatically.

The RTC clock registers are double-buffered to avoid access of incorrect data that can occur

during clock update cycles. The double-buffered system also prevents time loss as the

timekeeping countdown continues unabated by access to time register data. The DS1742 also

contains its own power-fail circuitry, which deselects the device when the V

CC

supply is in an

out-of-tolerance condition. This feature prevents loss of data from unpredictable system

operation brought on by low V

CC

as errant access and update cycles are avoided.

DS1742

3 of 16

CLOCK OPERATIONS—READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data,

internal updates to the DS1742 clock registers should be halted before clock data is read to

prevent reading of data in transition. However, halting the internal clock register updating

process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit,

bit 6 of the century register, see Table 2. As long as a 1 remains in that position, updating is

halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was

current at the moment the halt command was issued. However, the internal clock registers of

the double-buffered system continue to update so that the clock accuracy is not affected by the

access of data. All of the DS1742 registers are updated simultaneously after the internal clock

register updating process has been re-enabled. Updating is within a second after the read bit is

written to 0. The READ bit must be a zero for a minimum of 500s to ensure the external

registers will be updated.

Figure 1. DS1742 BLOCK DIAGRAM

Table 1. TRUTH TABLE

V

CC

CE

OE

WE

MODE DQ POWER

V

IH

X Deselect High-Z X Standby

V

IL

X V

IL

Write Data In Active

V

IL

V

IL

V

IH

Read Data Out Active

V

CC

> V

PF

V

IL

V

IH

V

IH

Read High-Z Active

V

SO

< V

CC

< V

PF

Deselect CMO dby X X X High-Z S Stan

V

CC

< V

SO

< V

PF

X X X Deselect High-Z Data Retention Mode

DS1742-100IND+

DS1742-100IND+

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