DS1742-100IND+ Datasheet DS1742W-150+, DS1742-100, DS1742-100IND+ | P4-P6

DS1742

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SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like

the read bit, halts updates to the DS1742 registers. The user can then load them with the

correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then

transfers those values to the actual clock counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be

turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the

seconds registers, see Table 2. Setting it to a 1 stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit

is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512

Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency

as long as conditions for access remain valid (i.e., CE low, low, OE WE high, and address for

seconds register remain valid and stable).

CLOCK ACCURACY

The DS1742 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. Dallas

Semiconductor calibrates the RTC at the factory using nonvolatile tuning elements. The

DS1742 does not require additional calibration. For this reason, methods of field clock

calibration are not available and not necessary. Clock accuracy is also affected by the electrical

environment and caution should be taken to place the RTC in the lowest level EMI section of

the PCB layout. For additional information refer to Application Note 58.

Table 2. REGISTER MAP

DATA

ADDRES

FUNCTION RANGE

7FF 10 Year Year Year 00–99

7FE X X X

Month

Month Month 01–12

7FD X X 10 Date Date Date 01–31

7FC BF FT X X X Day Day 01–07

7FB X X 10 Hour Hour Hour 00–23

7FA X 10 Minutes Minutes Minutes 00–59

7F9

OSC

10 Seconds Seconds Seconds 00–59

7F8 W R 10 Century Century Control 00–39

OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG

Note: All indicated “X” bits are not used but must be set to “0” during write cycle to ensure proper clock operation.

DS1742

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RETRIEVING DATA FROM RAM OR CLOCK

The DS1742 is in the read mode wheneve

(output enable) is low,

(write enable) is

high, and CE (chip enable) is low. The device architecture allows ripple-through access to any

of the address locations in the NV SRAM. Valid data will be available at the DQ pins within t

after the last address input is stable, providing that the

C E and OE access times and states are

satisfied. If or

CE OE

access times and states are not met, valid data will be available at the

latter of chip enable access (t

CEA

) or at output enable access time (t

OEA

). The state of the data

input/output pins (DQ) is controlled by , and CE OE . If the outputs are activated before t

, the

data lines are driven to an intermediate state until t

. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for output data hold time (t

) but will then

go indeterminate until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1742 is in the write mode whenever and WE CE are in their active state. The start of a

write is referenced to the latter occurring transition of on CEWE . The addresses must be held

valid throughout the cycle. or

CE WE

must return inactive for a minimum of t

prior to the

initiation of another read or write cycle. Data in must be valid t

prior to the end of write and

remain valid for t

afterward. In a typical application, the OE signal will be high during a write

cycle. However, OE can be active provided that care is taken with the data bus to avoid bus

contention. If is low prior to

OE WE

transitioning low the data bus can become active with read

data defined by the address inputs. A low transition on WE will then disable the outputs t

WEZ

after goes active. WE

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when VCC is greater than

. However, when VCC is below the power fail point, V

, (point at which write protection

occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls

below the battery switch point V

(battery supply level), device power is switched from the VCC

pin to the backup battery. RTC operation and SRAM data are maintained from the battery until

CC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or

read only when V

CC is greater than V

. When VCC falls below the power fail point, V

, access to

the device is inhibited. If V

is less than Vso, the device power is switched from VCC to the

backup supply (V

BAT

) when V

drops below V

. If V

is greater than Vso, the device power is

switched from V

CC to the backup supply (V

BAT

) when VCC drops below Vso. RTC operation and

SRAM data are maintained from the battery until V

is returned to nominal levels.

DS1742

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BATTERY LONGEVITY

The DS1742 has a lithium power source that is designed to provide energy for clock activity,

and clock and RAM data retention when the V

supply is not present. The capability of this

internal power supply is sufficient to power the DS1742 continuously for the life of the

equipment in which it is installed. For specification purposes, the life expectancy is 10 years at

25°C with the internal clock oscillator running in the absence of V

power. Each DS1742 is

shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing

full energy capacity. When V

is first applied at a level greater than V

, the lithium energy

source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be

much longer than 10 years since no lithium battery energy is consumed when V

is present.

BATTERY MONITOR

The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit

(bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not

writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium

energy source is indicated and both the contents of the RTC and RAM are questionable.

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