AD5626
Rev. A | Page 9 of 20
10
0.01
10 100k
06757-020
FREQUENCY (Hz)
OUTPUT NOISE DENSITY (µV/Hz)
100 1k 10k
0.1
1
V
DD
= 5V
NO LOAD
DATA = 0xFFF
60
0
–12
06757-017
TOTAL UNADJUSTED ERROR (mV)
NNUMBER OF UNITS
50
40
30
20
10
–8 –4 0 4 8 12
TUE = INL + ZS + FS
SS = 300 UNITS
T
A
= 25°C
Figure 17. Total Unadjusted Error Histogram
Figure 20. Output Voltage Noise vs. Frequency
4.115
4.075
–50 125
06757-018
TEMPERATURE (°C)
FULL-SCALE OUTPUT (V)
4.110
4.105
4.100
4.095
4.090
4.085
4.080
–25 0 25 50 75 100
V
DD
= 5V
NO LOAD
SS = 300 UNITS
AVG + 3
AVG
AVG – 3
5
–5
01
06757-021
HOURS OF OPERATION AT 125°C
OUTPUT VOLTAGE CHANGE (mV)
200
4
3
2
1
0
–1
–2
–3
–4
200 400 600 800 1000
135 UNITS TESTED
AVERAGE
RANGE
READINGS NORMALIZED
TO ZERO HOUR TIME POINT
Figure 18. Full-Scale Output Voltage vs. Temperature
Figure 21. Long-Term Drift Accelerated by Burn-In
0.50
0.35
0.40
0.45
0.30
0.25
0.20
0.15
0.10
0.05
0
–40
06757-019
TEMPERATURE (°C)
ZERO SCALE (mV)
–20 0 20 40 60 80
1.6
0
–40
06757-022
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
200 20406080
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
DD
= 4.75V
V
DD
= 5V
V
DD
= 5.25V
Figure 19. Zero-Scale Voltage vs. Temperature Figure 22. Supply Current vs. Temperature
AD5626
Rev. A | Page 10 of 20
THEORY OF OPERATION
The AD5626 is a complete, ready-to-use, 12-bit digital-to-analog
converter (DAC). It contains a voltage-switched, 12-bit, laser-
trimmed DAC, a curvature-corrected band gap reference, a
rail-to-rail output op amp, a DAC register, and a serial data
input register. The serial data interface consists of an SCLK,
serial data in (SDIN), and a load strobe (
LDAC
). This basic
3-wire interface offers maximum flexibility for interface to the
widest variety of serial data input loading requirements. In
addition, a
CS
select is provided for multiple packaging loading
and a power-on-reset
CLR
pin to simplify start or periodic resets.
DAC SECTION
The DAC is a 12-bit voltage mode device with an output that
swings from the GND potential to the 2.5 V internal band gap
voltage. It uses a laser trimmed, rail-to-rail ladder which is
switched by N-channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output internally connects to the rail-to-rail
output op amp.
AMPLIFIER SECTION
A low power consumption, precision amplifier buffers the DAC
output. This amplifier contains a differential PNP pair input
stage that provides low offset voltage and low noise, as well as
the ability to amplify the zero-scale DAC output voltages.
The rail-to-rail amplifier is configured with a gain of 1.6384
(= 4.095 V/2.5 V) to set the 4.095 V full-scale output (1 mV/LSB).
See Figure 23 for an equivalent circuit schematic of the analog
section.
06757-023
2R
2R
2R
R2
R
2R
2R
R
R1
V
OUT
BUFFER
BAND GAP
REFERENCE
2.5V
SPDT
N-CHANNEL FET
SWITCHES
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
A
V
= 1.638
(= 4.095V/2.5V)
V
OLTAGE SWITCHED 12-BIT
RAIL-TO-RAIL CONVERTER
Figure 23. Equivalent AD5626 Schematic of Analog Section
The op amp has a 16 μs typical settling time to 0.01%. There are
slight differences in settling time for negative slewing signals vs.
positive slewing signals. See the oscilloscope photos in the
Typical Performance Characteristics section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier is designed to
provide precision performance when operating near either
power supply.
06757-024
P-CH
V
DD
V
OUT
AGND
N-CH
Figure 24. Equivalent Analog Output Circuit
Figure 24 shows an equivalent output schematic of the rail-to-
rail amplifier with its N-channel pull-down FETs that pull an
output load directly to GND. The output sourcing current is
provided by a P-channel pull-up device that can supply GND
terminated loads, especially at the low supply tolerance values
of 4.75 V. Figure 5 and Figure 6 provide information on output
swing performance near ground and full-scale as a function of
load. In addition to resistive load driving capability, the amplifier
has also been carefully designed and characterized for up to
500 pF capacitive load driving capability.
POWER SUPPLY
The very low power consumption of the AD5626 is a direct
result of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
For power consumption sensitive applications, it is important
to note that the internal power consumption of the AD5626
is strongly dependent on the actual logic input voltage levels
present on the SDIN,
CS
,
LDAC
, and
CLR
pins. Because these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving
Logic V
OH
and Logic V
OL
voltage levels. The graph in
shows the effect on total AD5626 supply current as a function
of the actual value of input logic voltage. Consequently, use of
CMOS logic vs. TTL minimizes power dissipation in the static
state. A V
IL
= 0 V on the SDIN,
Figure 9
CS
, and
CLR
pins provides the
lowest standby power dissipation of 2.5 mW (500 μA × 5 V).
As with any analog system, it is recommended that the AD5626
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection vs. frequency
performance. This should be taken into account when using higher
frequency, switched mode power supplies with ripple frequencies
of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
AD5626 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
4.75 V to 5.25 V. If reduced linearity and source current capa-
bility near full scale can be tolerated, operation of the AD5626
is possible down to 4.3 V. The minimum operating supply
AD5626
Rev. A | Page 11 of 20
voltage vs. load current plot, shown in Figure 11, provides
information for operation below V
DD
= 4.75 V.
TIMING AND CONTROL
The AD5626 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC
output voltage. After the new value is fully loaded in the serial
input register, it can be asynchronously transferred to the DAC
register by strobing the
LDAC
pin. The DAC register uses a
level sensitive
LDAC
strobe that should be returned high before
any new data is loaded into the serial input register. At any time,
the contents of the DAC register can be reset to zero by strobing
the
CLR
pin that causes the DAC output voltage to go to zero
volts. details all of the timing requirements together
with , the control logic truth table.
Figure 2
Table 5

AD5626BCPZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 5V 12-Bit SPI Interface
Lifecycle:
New from this manufacturer.
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