NCP1271P100G Datasheet NCP1271D100R2G, NCP1271D65R2G, NCP1271ADAPGEVB | P10-P12

NCP1271

http://onsemi.com

OPERATING DESCRIPTION

Introduction

The NCP1271 represents a new generation of the

fixed−frequency PWM current−mode flyback controllers

from ON Semiconductor. The device features integrated

high−voltage startup and excellent standby performance.

The proprietary Soft−Skip Mode achieves extremely

low−standby power consumption while keeping power

supply acoustic noise to a minimum. The key features of

the NCP1271 are as follows:

• Timer−Based Fault Detection: In the event that an

abnormally large load is applied to the output for more

than 130 ms, the controller will safely shut the

application down. This allows accurate overload (OL)

or short−circuit (SC) detection which is not dependent

on the auxiliary winding.

• Soft−Skip Mode: This proprietary feature of the

NCP1271 minimizes the standby low−frequency

acoustic noise by ramping the peak current envelope

whenever skip is activated.

• Adjustable Skip Threshold: This feature allows the

power level at which the application enters skip to be

fully adjusted. Thus, the standby power for various

applications can be optimized. The default skip level

is 1.2 V (40% of the maximum peak current)

• 500 V High−Voltage Startup Capability: This

AC−DC application friendly feature eliminates the

need for an external startup biasing circuit, minimizes

the standby power loss, and saves printed circuit board

(PCB) space.

• Dual High−Voltage Startup−Current Levels: The

NCP1271 uniquely provides the ability to reduce the

startup current supply when Vcc is low. This prevents

damage if Vcc is ever shorted to ground. After Vcc

rises above approximately 600 mV, the startup current

increases to its full value and rapidly charges the Vcc

capacitor.

• Latched Protection: The NCP1271 provides a pin,

which if pulled high, places the part in a latched off

mode. Therefore, overvoltage (OVP) and

overtemperature (OTP) protection can be easily

implemented. A noise filter is provided on this function

to reduce the chances of falsely triggering the latch. The

latch is released when Vcc is cycled below 4 V.

• Non−Latched Protection/ Shutdown Option: By

pulling the feedback pin below the skip threshold

level, a non−latching shutdown mode can be easily

implemented.

• 4.0 ms Soft−Start: The soft start feature slowly ramps

up the drive duty cycle at startup. This forces the

primary current to also ramp up slowly and

dramatically reduces the stress on power components

during startup.

• Current−Mode Operation: The NCP1271 uses

current−mode control which provides better transient

response than voltage−mode control. Current−mode

control also inherently limits the cycle−by−cycle

primary current.

• Compensation Ramp: A drawback of current−mode

regulation is that the circuit may become unstable

when the operating duty cycle is too high. The

NCP1271 offers an adjustable compensation ramp to

solve this instability.

• 80% Maximum Duty Cycle Protection: This feature

limits the maximum on time of the drive to protect the

power MOSFET from being continuously on.

• Frequency Jittering: Frequency jittering softens the

EMI signature by spreading out peak energy within a

band +/− 7.5% from the center frequency.

• Switching Frequency Options: The NCP1271 is

available in either 65 kHz or 100 kHz fixed frequency

options. Depending on the application, the designer

can pick the right device to help reduce magnetic

switching loss or improve the EMI signature before

reaching the 150 kHz starting point for more

restrictive EMI test limits.

NCP1271 Operating Conditions

There are 5 possible operating conditions for the NCP1271:

1. Normal Operation – When V

is above V

CC(off)

(9.1 V typical) and the feedback pin voltage (V

)

is within the normal operation range (i.e.,V

< 3.0

V), the NCP1271 operates as a fixed−frequency

current−mode PWM controller.

2. Standby Operation (or Skip−Cycle Operation)

When the load current drops, the compensation

network responds by reducing the primary peak

current. When the peak current reaches the skip

peak current level, the NCP1271 enters Soft−Skip

operation to reduce the power consumption. This

Soft−Skip feature offers a modified peak current

envelope and hence also reduces the risk of audible

noise. In the event of a sudden load increase, the

transient load detector (TLD) disables Soft−Skip

and applies maximum power to bring the output

into regulation as fast as possible.

3. Fault Operation – When no feedback signal is

received for 130 ms or when V

drops below

CC(off)

(9.1 V typical), the NCP1271 recognizes it

as a fault condition. In this fault mode, the Vcc

voltage is forced to go through two cycles of slowly

discharging and charging. This is known as a

“double hiccup.” The double hiccup insures that

ample time is allowed between restarts to prevent

overheating of the power devices. If the fault is

NCP1271

http://onsemi.com

cleared after the double hiccup, then the application

restarts. If not, then the process is repeated.

4. Latched Shutdown – When the Skip/latch pin (Pin

1) voltage is pulled above 8.0 V for more than

13 ms, the NCP1271 goes into latchoff shutdown.

The output is held low and V

stays in hiccup

mode until the latch is reset. The reset can only

occur if Vcc is allowed to fall below V

CC(reset)

(4.0 V typical). This is generally accomplished by

unplugging the main input AC source.

5. Non−Latched Shutdown – If the FB pin is pulled

below the skip level, then the device will enter a

non−latched shutdown mode. This mode disables

the driver, but the controller automatically recovers

when the pulldown on FB is released. Alternatively,

Vcc can also be pulled low (below 190 mV) to

shutdown the controller. This has the added benefit

of placing the part into a low current consumption

mode for improved power savings.

Biasing the Controller

During startup, the Vcc bias voltage is supplied by the

HV Pin (Pin 8). This pin is capable of supporting up to

500 V, so it can be connected directly to the bulk capacitor.

Internally, the pin connects to a current source which

rapidly charges V

to its V

CC(on)

threshold. After this

level is reached, the controller turns on and the transformer

auxiliary winding delivers the bias supply voltage to V

CC.

The startup FET is then turned off, allowing the standby

power loss to be minimized. This in−chip startup circuit

minimizes the number of external components and Printed

Circuit Board (PCB) area. It also provides much lower

power dissipation and faster startup times when compared

to using startup resistors to V

. The auxiliary winding

needs to be designed to supply a voltage above the V

CC(off)

level but below the maximum V

level of 20 V.

For added protection, the NCP1271 also include a dual

startup mode. Initially, when V

is below the inhibit

voltage V

inhibit

(600 mV typical), the startup current source

is small (200 uA typical). The current goes higher (4.1 mA

typical) when V

goes above V

inhibit

. This behavior is

illustrated in Figure 23. The dual startup feature protects

the device by limiting the maximum power dissipation

when the V

pin (Pin 6) is accidentally grounded. This

slightly increases the total time to charge V

, but it is

generally not noticeable.

Figure 23. Startup Current at Various V

Levels

CC(on)

4.1 mA

200 uA

Startup current

0.6 V

CC(latch)

Double Hiccup Mode

Figure 24 illustrates the block diagram of the startup

circuit. An undervoltage lockout (UVLO) comparator

monitors the V

supply voltage. If V

falls below

CC(off)

, then the controller enters “double hiccup mode.”

Figure 24. V

Management

Vcc

12.6/

5.8 V

9.1 V

turn off

UVLO

−

turn on internal bias

double

hiccup

20V

4.1 mA when Vcc > 0.6 V

200 uA when Vcc < 0.6 V

10−to−20V biasing voltage

(available after startup)

Counter

bulk

During double hiccup operation, the Vcc level falls to

CC(latch)

(5.8 V typical). At this point, the startup FET is

turned back on and charges V

to V

CC(on)

(12.6 V typical).

then slowly collapses back to the V

CC(latch)

level. This

cycle is repeated twice to minimize power dissipation in

NCP1271

http://onsemi.com

external components during a fault event. After the second

cycle, the controller tries to restart the application. If the

restart is not successful, then the process is repeated.

During this mode, V

never drops below the 4 V latch

reset level. Therefore, latched faults will not be cleared

unless the application is unplugged from the AC line (i.e.,

bulk

discharges).

Figure 25 shows a timing diagram of the V

double

hiccup operation. Note that at each restart attempt, a soft

start is issued to minimize stress.

Figure 25. V

Double Hiccup Operation in a Fault

Condition

5.8 V

12.6 V

9.1 V

startup

time

Supply voltage, V

time

Drain current, I

Switching is missing in

every two V

hiccup cycles

featuring a “double−hiccup”

Capacitor

As stated earlier, the NCP1271 enters a fault condition

when the feedback pin is open (i.e. FB is greater than 3 V)

for 130 ms or V

drops below V

CC(off)

(9.1 V typical).

Therefore, to take advantage of these features, the V

capacitor needs to be sized so that operation can be

maintained in the absence of the auxiliary winding for at

least 130 ms.

The controller typically consumes 2.3 mA at a 65 kHz

frequency with a 1 nF switch gate capacitance. Therefore,

to ensure at least 130 ms of operation, equation 1 can be

used to calculate that at least an 85 mF capacitor would be

necessary.

startup

VCC

CC1

85 mF · (12.6 V−9.1 V)

2.3 mA

+ 130 ms

(eq. 1)

If the 130 ms timer feature will not be used, then the

capacitance value needs to at least be large enough for the

output to charge up to a point where the auxiliary winding

can supply V

. Figure 26 describes different startup

scenarios with different V

capacitor values. If the V

cap is too small, the application fails to start because the

bias supply voltage cannot be established before V

reduced to the V

CC(off)

level.

Figure 26. Different Startup Scenarios of the

Circuits with Different V

Capacitors

time

out

time

out

9.1 V

12.6 V

5.8 V

9.1 V

12.6 V

startup

0.6 V

Output waveforms with a large enough V

capacitor

Output waveforms with too small of a V

capacitor

Desired level of V

out

It is highly recommended that the V

capacitor be as

close as possible to the V

and ground pins of the product

to reduce switching noise. A small bypass capacitor on this

pin is also recommended. If the switching noise is large

enough, it could potentially cause V

to go below V

CC(off)

and force a restart of the controller.

It is also recommended to have a margin between the

winding bias voltage and V

CC(off)

so that all possible

transient swings of the auxiliary winding are allowed. In

standby mode, the V

voltage swing can be higher due to

the low−frequency skip−cycle operation. The V

capacitor also affects this swing. Figure 27 illustrates the

possible swings.

Figure 27. Timing Diagram of Standby Condition

9.1 V

skip

time

Supply voltage, V

time

Feedback pin voltage, V

time

Drain current, I

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

NCP1271P100G

Mfr. #:

Buy NCP1271P100G

Manufacturer:

ON Semiconductor

Description:

Switching Controllers ANA PMW CONTROLLER

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

NCP1271P100G

NCP1271P100G

Products related to this Datasheet