Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
2
1998 Sep 24 8533-2125 20079
FEATURES
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• All inputs have bushold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
• MULTIBYTE
TM
flow-through standard pin-out architecture
• Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16500 is a high-performance CMOS product.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OE
AB
and
OE
BA
), latch enable (LE
AB
and LE
BA
), and clock (CP
AB
and CP
BA
)
inputs. For A-to-B data flow, the device operates in the transparent
mode when LE
AB
is High. When LE
AB
is Low, the A data is latched if
CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus
data is stored in the latch/flip-flop on the High-to-Low transition of
CP
AB
. When OE
AB
is High, the outputs are active. When OE
AB
is
Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
. The output enables are complimentary (OE
AB
is active
High, and OE
BA
is active Low).
To ensure the high impedance state during power up or power
down, OE
BA
should be tied to V
CC
through a pullup resistor and
OE
AB
should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
= 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
3.1
2.9
ns
C
I/O
Input/output capacitance 8.0 pF
C
I
Input capacitance 4.0 pF
p
p
p
Outputs enabled 21
p
PD
I
=
CC
Outputs disabled 3
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
= C
PD
× V
CC
2
× f
i
+ (C
L
× V
CC
2
× f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
× V
CC
2
× f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16500 DGG SOT364-1
