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74ALVCH16500DGGS

P1-P3P4-P6P7-P9P10-P12P13-P15
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
1998 Sep 24
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
OE
AB
LE
AB
A0
GND
A1
A2
V
CC
A4
A5
GND
A6
A7
A8
A9
A3
A10
A11
GND
A12
A13
B13
B12
GND
B11
B10
B9
B8
B7
B6
GND
B5
B4
B3
V
CC
B2
B1
GND
A0
CP
AB
GND
21
22
23
24
33
34
35
36
A14
V
CC
A15
A16
B16
B15
V
CC
B14
25
26
27
28
29
30
31
32
GND
A17
OE
BA
LE
BA
GND
CP
BA
B17
GND
SW00080
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE
AB
Output enable A-to-B
2 LE
AB
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
20, 21, 23, 24,
26
A0 to A17 Data inputs/outputs
4, 11, 18, 25,
29, 32, 39, 46,
53, 56
GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage
27 OE
BA
Output enable B-to-A
28 LE
BA
Latch enable B-to-A
30 CP
BA
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0 to B17 Data inputs/outputs
55 CP
AB
Clock input A-to-B
BUS HOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00044
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
1998 Sep 24
4
LOGIC SYMBOL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OE
AB
LE
AB
CP
AB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OE
BA
LE
BA
CP
BA
3
5
6
8
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
9
SW00081
LOGIC SYMBOL (IEEE/IEC)
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D 1 1
416D
1
56
2
27
30
28
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
SW00082
OE
AB
CP
AB
LE
AB
OE
AB
CP
BA
LE
BA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
Philips Semiconductors Product specification
74ALVCH1650018-bit universal bus transceiver (3-State)
1998 Sep 24
5
LOGIC DIAGRAM (one section)
C1
1D
C1
1D
C1
1D
C1
1D
18 IDENTICAL CHANNELS
An
OE
BA
LE
AB
CP
AB
LE
BA
CP
BA
OE
AB
Bn
SW00090
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
OEAB LEAB CPAB An Bn
L H X X Z Disabled
H H X H H
Transparent
H H X L L
H ↓ X h H
Latch data & dis
p
lay
H ↓ X I L
Latch
data
&
dis lay
H L ↓ h H
Clock data & dis
p
lay
H L ↓ I L
Clock
data
&
dis lay
H L H or L X H
Hold data & dis
p
lay
H L H or L X L
Hold
data
&
dis lay
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance ”off” state
↓ = High-to-Low Enable or Clock transition
P1-P3P4-P6P7-P9P10-P12P13-P15

74ALVCH16500DGGS

Mfr. #:
Buy 74ALVCH16500DGGS
Manufacturer:
Nexperia
Description:
Bus Transceivers 18-Bit Universal Bus Transceiver, 3-State
Lifecycle:
New from this manufacturer.
Delivery:
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