MAX1777/MAX1977/MAX1999
High-Efficiency, Quad Output, Main Power-
Supply Controllers for Notebook Computers
22 ______________________________________________________________________________________
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. This algorithm allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. There must be
low-resistance, low-inductance paths from the gate dri-
vers to the MOSFET gates for the adaptive dead-time cir-
cuit to work properly. Otherwise, the sense circuitry
interprets the MOSFET gate as “off” when there is actual-
ly charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50mils to 100mils wide if
the MOSFET is 1in from the device).
POR, UVLO, and Internal Digital
Soft-Start
Power-on reset (POR) occurs when V+ rises above
approximately 1V, resetting the undervoltage, over-
voltage, and thermal-shutdown fault latches. LDO5
undervoltage lockout (UVLO) circuitry inhibits switching
when LDO5 is below 4V. DL_ is low if PRO is disabled;
DL_ is high if PRO is enabled. The output voltages
begin to ramp up as LDO5 rises above 4V. The internal
digital soft-start timer begins to ramp up the maximum
allowed current limit during startup. The 1.7ms ramp
occurs in five steps: 20%, 40%, 60%, 80%, and 100%.
Power-Good Output (PGOOD)
The PGOOD comparator continuously monitors both out-
put voltages for undervoltage conditions. PGOOD is
actively held low in shutdown, standby, and soft-start.
PGOOD releases and digital soft-start terminates when
both outputs reach the error-comparator threshold.
PGOOD goes low if either output turns off or is 10%
below its nominal regulation point. PGOOD is a true
open-drain output. Note that PGOOD is independent of
the state of PRO.
Fault Protection
The MAX1777/MAX1977/MAX1999 provide over/under-
voltage fault protection. Drive PRO low to activate fault
protection. Drive PRO high to disable fault protection.
Once activated, the devices continuously monitor for
both undervoltage and overvoltage conditions.
Overvoltage Protection
When the output voltage is 11% above the set voltage,
the overvoltage fault protection activates. The synchro-
nous rectifier turns on 100% and the high-side MOSFET
turns off. This rapidly discharges the output capacitors,
decreasing the output voltage. The output voltage may
dip below ground. For loads that cannot tolerate a neg-
ative voltage, place a power Schottky diode across the
output to act as a reverse-polarity clamp. In practical
applications, there is a fuse between the power source
(battery) and the external high-side switches. If the
overvoltage condition is caused by a short in the high-
side switch, turning the synchronous rectifier on 100%
creates an electrical short between the battery and
GND, blowing the fuse and disconnecting the battery
from the output. Once an overvoltage fault condition is
set, it can only be reset by toggling SHDN, ON_, or
cycling V+ (POR).
Undervoltage Protection
When the output voltage is 30% below the set voltage
for over 22ms (undervoltage shutdown blanking time),
the undervoltage fault protection activates. Both SMPSs
stop switching. The two outputs start to discharge (see
the Discharge Mode (Soft-Stop) section). When the out-
put voltage drops to 0.3V, the synchronous rectifiers
turn on, clamping the outputs to GND. Toggle SHDN,
ON_, or cycle V+ (POR) to clear the undervoltage fault
latch.
Thermal Protection
The MAX1777/MAX1977/MAX1999 have thermal shut-
down to protect the devices from overheating. Thermal
shutdown occurs when the die temperature exceeds
+160°C. All internal circuitry shuts down during thermal
shutdown. The MAX1777/MAX1977/MAX1999 may trig-
ger thermal shutdown if LDO_ is not bootstrapped from
OUT_ while applying a high input voltage on V+ and
drawing the maximum current (including short circuit)
from LDO_. Even if LDO_ is bootstrapped from OUT_,
overloading the LDO_ causes large power dissipation
on the bootstrap switches, which may result in thermal
shutdown. Cycling SHDN, ON3, or ON5, or a V+ (POR)
ends the thermal shutdown state.
Discharge Mode (Soft-Stop)
When PRO is low, and a transition to standby or shut-
down mode occurs, or the output undervoltage fault
latch is set, the outputs discharge to GND through an
internal 12 switch, until the output voltages decrease
to 0.3V. The reference remains active to provide an
accurate threshold and to provide overvoltage protec-
tion. When both SMPS outputs discharge to 0.3V, the
DL_ synchronous rectifier drivers are forced high. The
synchronous rectifier drivers clamp the SMPS outputs
to GND. When PRO is high, the SMPS outputs do not
discharge, and the DL_ synchronous rectifier drivers
remain low.
Shutdown Mode
Drive SHDN below the precise SHDN input falling-edge
trip level to place the MAX1777/MAX1977/MAX1999 in
its low-power shutdown state. The MAX1777/MAX1977/
MAX1999 consume only 6µA of quiescent current while
MAX1777/MAX1977/MAX1999
High-Efficiency, Quad Output, Main Power-
Supply Controllers for Notebook Computers
______________________________________________________________________________________ 23
in shutdown mode. When shutdown mode activates, the
reference turns off, making the threshold to exit shut-
down inaccurate. To guarantee startup, drive SHDN
above 2V (SHDN input rising-edge trip level). For auto-
matic shutdown and startup, connect SHDN to V+. If
PRO is low, both SMPS outputs are discharged to 0.3V
through a 12 switch before entering true shutdown.
The accurate 1V falling-edge threshold on SHDN can be
used to detect a specific analog voltage level and shut
the device down. Once in shutdown, the 1.6V rising-
edge threshold activates, providing sufficient hysteresis
for most applications. For additional hysteresis, the
undervoltage threshold can be made dependent on
REF or LDO_, which go to 0V in shutdown.
Power-Up Sequencing and
On/Off Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs.
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation and
starts after that output regulates. The second SMPS
remains on until the first SMPS turns off, the device shuts
down, a fault occurs, or LDO5 goes into undervoltage
lockout. Both supplies begin their power-down sequence
immediately when the first supply turns off. Driving ON_
MODE CONDITION COMMENT
Power-Up LDO5 < UVLO threshold
Transitions to discharge mode after a V+ POR and after REF becomes valid.
LDO5, LDO3, REF remain active. DL_ is active if PRO is low.
Run
SHDN = high, ON3 or ON5
enabled
Normal operation
Overvoltage
Protection
Either output > 111% of
nominal level, PRO = low
DL_ is forced high. LDO3, LDO5 active. Exited by a V+ POR or by toggling
SHDN, ON3, or ON5.
Undervoltage
Protection
Either output < 70% of
nominal after 22ms time-
out expires and output is
enabled, PRO = low
If PRO is low, DL_ is forced high after discharge mode terminates. LDO3,
LDO5 active. Exited by a V+ POR or by toggling SHDN, ON3, or ON5.
Discharge
PRO is low and either
SMPS output is still high in
either standby mode or
shutdown mode
Discharge switch (12) connects OUT_ to PGND. One output may still run
while the other is in discharge mode. Activates when LDO_ is in UVLO, or
transition to UVLO, standby, or shutdown has begun. LDO3, LDO5 active.
Standby
ON5, ON3 < startup
threshold, SHDN = high
DL_ stays high if PRO is low. LDO3, LDO5 active.
Shutdown SHDN = low All circuitry off
Thermal Shutdown
T
J
> +160°C All circuitry off. Exited by V+ POR or cycling SHDN, ON3, or ON5.
Table 3. Operating Mode Truth Table
SHDN (V) V
ON3
(V) V
ON5
(V) LDO5 LDO3 5V SMPS 3V SMPS
< 1.0 X X Off Off Off Off
> 2.4 < 1.6 < 1.6 On On Off Off
> 2.4 > 2.4 > 2.4 On On On On
> 2.4 > 2.4 < 1.6 On On Off On
> 2.4 < 1.6 > 2.4 On On On Off
> 2.4 > 2.4 REF On On
On (after 3V
SMPS is up)
On
> 2.4 REF > 2.4 On On On
On (after 5V
SMPS is up)
Table 4. Power-Up Sequencing
MAX1777/MAX1977/MAX1999
High-Efficiency, Quad Output, Main Power-
Supply Controllers for Notebook Computers
24 ______________________________________________________________________________________
below 0.8V clears the overvoltage, undervoltage, and
thermal fault latches.
Adjustable-Output Feedback
(Dual-Mode FB)
Connect FB_ to GND to enable the fixed, preset SMPS
output voltages (3.3V and 5V). Connect a resistive volt-
age-divider at FB_ between OUT_ and GND to adjust
the respective output voltage between 2V and 5.5V
(Figure 11). Choose R2 to be about 10k and solve for
R1 using the equation:
where V
FB
= 2V nominal.
When using the adjustable output mode, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to OUT5
through an internal switch only when OUT5 is above the
LDO5 bootstrap-switch threshold (4.56V). LDO3 con-
nects to OUT3 through an internal switch only when
OUT3 is above the LDO3 bootstrap switch threshold
(2.91V). Bootstrapping is most effective when the fixed
output voltages are used. Once LDO_ is bootstrapped
from OUT_, the internal linear regulator turns off. This
reduces internal power dissipation and improves effi-
ciency when LDO_ is powered with a high input voltage.
Design Procedure
Establish the input voltage range and maximum load
current before choosing an inductor and its associated
ripple-current ratio (LIR). The following four factors dic-
tate the rest of the design:
1) Input Voltage Range. The maximum value (V+
(MAX)
)
must accommodate the maximum AC adapter volt-
age. The minimum value (V+
(MIN)
) must account for
the lowest input voltage after drops due to connec-
tors, fuses, and battery selector switches. Lower input
voltages result in better efficiency.
2) Maximum Load Current. The peak load current
(I
LOAD(MAX)
) determines the instantaneous compo-
nent stress and filtering requirements, and thus dri-
ves output capacitor selection, inductor saturation
rating, and the design of the current-limit circuit.
The continuous load current (I
LOAD
) determines the
thermal stress and drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage and MOSFET switching losses. The
MAX1777 has a nominal switching frequency of
200kHz for the 5V SMPS and 300kHz for the 3.3V
SMPS. The MAX1977 has a nominal switching fre-
quency of 400kHz for the 5V SMPS and 500kHz for
the 3.3V SMPS. The MAX1999 has pin-selectable
switching frequency.
4) Inductor Ripple Current Ratio (LIR). LIR is the
ratio of the peak-peak ripple current to the average
inductor current. Size and efficiency trade-offs must
be considered when setting the inductor ripple cur-
rent ratio. Low inductor values cause large ripple
currents, resulting in the smallest size, but poor effi-
ciency and high output noise. The minimum practi-
cal inductor value is one that causes the circuit to
operate at critical conduction (where the inductor
current just touches zero with every cycle at maxi-
mum load). Inductor values lower than this grant no
further size reduction benefit.
The MAX1777/MAX1977/MAX1999s’ pulse-skipping
algorithm (SKIP = GND) initiates skip mode at the
critical conduction point. So the inductor’s operat-
ing point also determines the load current at which
PWM/PFM switchover occurs. The optimum point is
usually found between 20% and 50% ripple current.
RR
V
V
OUT
FB
12 1
_
MAX1777
MAX1977
MAX1999
DH_
DL_
GND
OUT_
FB_
V+
R1
R2
V
OUT_
Figure 11. Setting V
OUT_
with a Resistor-Divider

MAX1777EEI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Quad-Out Main Power Sply Ctlr for Ntbk
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