MAX1777EEI+ Datasheet MAX1977EEI+, MAX1977EEI+T, MAX1999EEI+T | P25-P27

MAX1777/MAX1977/MAX1999

High-Efficiency, Quad Output, Main Power-

Supply Controllers for Notebook Computers

______________________________________________________________________________________ 25

Inductor Selection

The switching frequency (on-time) and operating point

(% ripple or LIR) determine the inductor value as follows:

Example: I

LOAD(MAX)

= 5A, V+ = 12V, V

OUT5

= 5V, f =

200kHz, 35% ripple current or LIR = 0.35:

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice. The core must be large enough

not to saturate at the peak inductor current (I

PEAK

= I

LOAD(MAX)

+ [(LIR/2) x I

LOAD(MAX)

]

The inductor ripple current also impacts transient-

response performance, especially at low V+ - V

OUT_

difference. Low inductor values allow the inductor cur-

rent to slew faster, replenishing charge removed from

the output filter capacitors by a sudden load step. The

peak amplitude of the output transient (V

SAG

) is also a

function of the maximum duty factor, which can be cal-

culated from the on-time and minimum off-time:

where minimum off-time = 0.350µs (max) and K is from

Table 2.

Determining the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

ley of the inductor current occurs at I

LOAD(MAX)

minus

half of the ripple current; therefore,

LIMIT(LOW)

> I

LOAD(MAX)

- [(LIR / 2) x I

LOAD(MAX)

]

where I

LIMIT(LOW)

= minimum current-limit threshold

voltage divided by the R

DS(ON)

of N2/N4 (MAX1999).

For the MAX1777/MAX1977/MAX1999, the minimum

current-limit threshold voltage is 93mV (ILIM_ = V

Use the worst-case maximum value for R

DS(ON)

from

the MOSFET N2/N4 data sheet and add some margin

for the rise in R

DS(ON)

with temperature. A good gener-

al rule is to allow 0.5% additional resistance for each °C

of temperature rise.

Examining the 5A circuit example with a maximum

DS(ON)

= 12mΩ at high temperature reveals the following:

LIMIT(LOW)

= 93mV / 12mΩ > 5A - (0.35 / 2) 5A

7.75A > 4.125A

7.75A is greater than the valley current of 4.125A, so

the circuit can easily deliver the full-rated 5A using the

fixed 100mV nominal current-limit threshold voltage.

Connect the source of the synchronous rectifier to a

current-sense resistor to GND (MAX1777/MAX1977),

and connect CS_ to that junction to set the current limit

for the device. The MAX1777/MAX1977/MAX1999 limit

the current with the sense resistor instead of the

DS(ON)

of N2/N4. The maximum value of the sense

resistor can be calculated with the equation

LIM_

= 93mV / R

SENSE

Output Capacitor Selection

The output filter capacitor must have low enough equiv-

alent series resistance (ESR) to meet output ripple and

load-transient requirements, yet have high enough ESR

to satisfy stability requirements. The output capaci-

tance must also be high enough to absorb the inductor

energy while transitioning from full-load to no-load con-

ditions without tripping the overvoltage fault latch. In

applications where the output is subject to large load

transients, the output capacitor’s size depends on how

much ESR is needed to prevent the output from dip-

ping too low under a load transient. Ignoring the sag

due to finite capacitance:

where V

DIP

is the maximum tolerable transient voltage

drop. In non-CPU applications, the output capacitor’s

size depends on how much ESR is needed to maintain

an acceptable level of output voltage ripple:

where V

P-P

is the peak-to-peak output voltage ripple.

The actual capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. Thus, the

capacitor is usually selected by ESR and voltage rating

rather than by capacitance value (this is true of tanta-

lum, OS-CON, and other electrolytic-type capacitors).

LIR I

ESR

LOAD MAX

≤

−

()

ESR

DIP

LOAD MAX

≤

()

ILK

CVK

SAG

LOAD MAX

OUT

OFF MIN

OUT OUT

OUT

OFF MIN

∆

()

⎛

⎝

⎜

⎞

⎠

⎟

××

+−

⎛

⎝

⎜

⎞

⎠

⎟

−

⎡

⎣

⎢

⎤

⎦

()

VVV

V kHz A

−

()

×××

512 5

12 200 0 35 5

. µ

VVV

V f LIR I

OUT OUT

LOAD MAX

+−

()

+× × ×

()

MAX1777/MAX1977/MAX1999

High-Efficiency, Quad Output, Main Power-

Supply Controllers for Notebook Computers

26 ______________________________________________________________________________________

When using low-capacity filter capacitors such as

polymer types, capacitor size is usually determined by

the capacity required to prevent V

SAG

and V

SOAR

from

tripping the undervoltage and overvoltage fault latches

during load transients in ultrasonic mode .

For low input-to-output voltage differentials (V

OUT

<2),

additional output capacitance is required to maintain sta-

bility and good efficiency in ultrasonic mode.

The amount of overshoot due to stored inductor energy

can be calculated as:

where I

PEAK

is the peak inductor current.

Stability Considerations

Stability is determined by the value of the ESR zero

ESR

) relative to the switching frequency (f). The point

of instability is given by the following equation:

where:

For a typical 300kHz application, the ESR zero frequen-

cy must be well below 95kHz, preferably below 50kHz.

Low-ESR capacitors (especially polymer or tantalum),

in widespread use at the time of publication, typically

have ESR zero frequencies lower than of 30kHz. In the

design example used for inductor selection, the ESR

needed to support a specified ripple voltage is found

by the equation:

where LIR is the inductor ripple current ratio and I

LOAD

is the average DC load. Using a LIR = 0.35 and an

average load current of 5A, the ESR needed to support

50mV

P-P

ripple is 28mΩ.

Do not place high-value ceramic capacitors directly

across the fast-feedback inputs (OUT_ to GND for inter-

nal feedback, FB_ divider point for external feedback)

without taking precautions to ensure stability. Large

ceramic capacitors can have a high-ESR zero frequency

and cause erratic, unstable operation. Adding a discrete

resistor or placing the capacitors a couple of inches

downstream from the junction of the inductor and OUT_

may improve stability.

Unstable operation manifests itself in two related but

distinctly different ways: double pulsing and fast-feed-

back loop instability. Noise on the output or insufficient

ESR may cause double pulsing. Insufficient ESR does

not allow the amplitude of the voltage ramp in the output

signal to be large enough. The error comparator mistak-

enly triggers a new cycle immediately after the 350ns

minimum off-time period has expired. Double pulsing

results in increased output ripple, and can indicate the

presence of loop instability caused by insufficient ESR.

Loop instability results in oscillations or ringing at the

output after line or load perturbations, causing the out-

put voltage to fall below the tolerance limit.

The easiest method for checking stability is to apply a

very fast zero-to-max load transient (refer to the

MAX1999 EV kit data sheet) and observe the output

voltage-ripple envelope for overshoot and ringing.

Monitoring the inductor current with an AC current

probe may also provide some insight. Do not allow

more than one cycle of ringing of under- or overshoot

after the initial step response.

Input Capacitor Selection

The input capacitors must meet the input ripple current

RMS

) requirement imposed by the switching current.

The MAX1777/MAX1977/MAX1999 dual switching regu-

lators operate at different frequencies. This interleaves

the current pulses drawn by the two switches and

reduces the overlap time where they add together. The

input RMS current is much smaller in comparison than

with both SMPSs operating in phase. The input RMS cur-

rent varies with load and the input voltage.

The maximum input capacitor RMS current for a single

SMPS is given by:

when V+ = 2 x V

OUT_

(D = 50%), I

RMS

has maximum

current of I

LOAD

/2.

The ESR of the input capacitor is important for deter-

mining capacitor power dissipation. All the power

RMS

x ESR) heats up the capacitor and reduces effi-

ciency. Nontantalum chemistries (ceramic or OS-CON)

are preferred due to their low ESR and resilience to

power-up surge currents. Choose input capacitors that

exhibit less than +10°C temperature rise at the RMS

input current for optimal circuit longevity. Place the

drains of the high-side switches close to each other to

share common input bypass capacitors.

VVV

RMS LOAD

OUT OUT

≈

+−

()

⎛

⎝

⎜

⎞

⎠

⎟

ESR

LIR I

RIPPLE P P

LOAD

()

−

ESR

ESR OUT

×× ×

2 π

ESR

≤

SOAR

PEAK

OUT

××

MAX1777/MAX1977/MAX1999

High-Efficiency, Quad Output, Main Power-

Supply Controllers for Notebook Computers

______________________________________________________________________________________ 27

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

(>5A) when using high-voltage (>20V) AC adapters.

Low-current applications usually require less attention.

Choose a high-side MOSFET (N1/N3) that has conduc-

tion losses equal to the switching losses at the typical

battery voltage for maximum efficiency. Ensure that the

conduction losses at the minimum input voltage do not

exceed the package thermal limits or violate the overall

thermal budget. Ensure that conduction losses plus

switching losses at the maximum input voltage do not

exceed the package ratings or violate the overall ther-

mal budget.

Choose a synchronous rectifier (N2/N4) with the lowest

possible R

DS(ON)

. Ensure the gate is not pulled up by the

high-side switch turning on due to parasitic drain-to-gate

capacitance, causing cross-conduction problems.

Switching losses are not an issue for the synchronous

rectifier in the buck topology, since it is a zero-voltage

switched device when using the buck topology.

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

extremes. For the high-side MOSFET, the worst-case

power dissipation (PD) due to the MOSFET’s R

DS(ON)

occurs at minimum battery voltage:

Generally, a small high-side MOSFET reduces switch-

ing losses at high input voltage. However, the R

DS(ON)

required to stay within package power-dissipation limits

often limits how small the MOSFET can be. The opti-

mum situation occurs when the switching (AC) losses

equal the conduction (R

DS(ON)

) losses.

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum battery volt-

age is applied, due to the squared term in the CV

✕ f

switching loss equation. Reconsider the high-side

MOSFET chosen for adequate R

DS(ON)

at low battery

voltages if it becomes extraordinarily hot when subject-

ed to V+

(MAX)

Calculating the power dissipation in N1/N3 due to

switching losses is difficult since it must allow for quan-

tifying factors that influence the turn-on and turn-off

times. These factors include the internal gate resis-

tance, gate charge, threshold voltage, source induc-

tance, and PC board layout characteristics. The follow-

ing switching loss calculation provides only a very

rough estimate and is no substitute for bench evalua-

tion, preferably including verification using a thermo-

couple mounted on N1/N3:

where C

RSS

is the reverse transfer capacitance of

N1/N3 and I

GATE

is the peak gate-drive source/sink

current.

For the synchronous rectifier, the worst-case power dis-

sipation always occurs at maximum battery voltage:

The absolute worst case for MOSFET power dissipation

occurs under heavy overloads that are greater than

LOAD(MAX)

but are not quite high enough to exceed

the current limit and cause the fault latch to trip. To

protect against this possibility, “overdesign” the circuit

to tolerate:

LOAD

= I

LIMIT(HIGH)

+ (LIR / 2 ) x I

LOAD(MAX)

where I

LIMIT(HIGH)

is the maximum valley current

allowed by the current-limit circuit, including threshold

tolerance and resistance variation.

Rectifier Selection

Current circulates from ground to the junction of both

MOSFETs and the inductor when the high-side switch is

off. As a consequence, the polarity of the switching

node is negative with respect to ground. This voltage is

approximately -0.7V (a diode drop) at both transition

edges while both switches are off (dead time). The drop

is I

x R

DS(ON)

when the low-side switch conducts.

The rectifier is a clamp across the synchronous rectifier

that catches the negative inductor swing during the dead

time between turning the high-side MOSFET off and the

synchronous rectifier on. The MOSFETs incorporate a

high-speed silicon body diode as an adequate clamp

diode if efficiency is not of primary importance. Place a

Schottky diode in parallel with the body diode to reduce

the forward voltage drop and prevent the N2/N4 MOSFET

body diodes from turning on during the dead time.

Typically, the external diode improves the efficiency by

1% to 2%. Use a Schottky diode with a DC current rating

equal to one-third of the load current. For example, use

PD N N

OUT

MAX

LOAD DS

24 1

()

=−

⎛

⎝

⎜

⎞

⎠

⎟

××

PD N N switching

CV fI

RSS MAX LOAD

GATE

()

×+ ××

⎛

⎝

⎜

⎞

⎠

⎟

PD N N resis ce

OUT

MIN

LOAD DS ON

( / tan )

()

⎛

⎝

⎜

⎞

⎠

⎟

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MAX1777EEI+

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