LA4032V-75TN44E Datasheet LA4032ZC-75TN48E, LA4032V-75TN44E, LA4064V-75TN48E | P4-P6

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

Figure 3. AND Array

Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term

cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total

5) product terms. The software automatically considers the availability and distribution of product term clusters as it

ﬁts the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path,

20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade tim-

ing variability for increased performance.

The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks:

• Product Term Allocator

• Cluster Allocator

• Wide Steering Logic

Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.

Figure 4. Macrocell Slice

PT0

PT1

Cluster 0

PT2

PT3

PT4

In[0]

In[34]

In[35]

Note:

Indicates programmable fuse.

PT80

PT81

PT82

Shared PT Clock

Shared PT Initialization

Shared PTOE

PT76

PT77

PT78

PT79

PT75

Cluster 15

n+1

n-1

n-2

from

n-1

from

n-4

from

n+2

from

n+1

5-PT

From

n-4

1-80

PTs

To n+4

Fast 5-PT

Path

To XOR (MC)

Cluster

Individual Product

Term Allocator

Cluster

Allocator

SuperWIDE™

Steering Logic

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

Product Term Allocator

The product term allocator assigns product terms from a cluster to either logic or control applications as required

by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-

ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated

with the cluster. Table 3 shows the available functions for each of the ﬁve product terms in the cluster. The OR gate

output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic

allocator.

Table 3. Individual PT Steering

Cluster Allocator

The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions

with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,

the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator

accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.

Table 4. Available Clusters for Each Macrocell

Wide Steering Logic

The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-

tor

+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions

and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term

chains.

Product Term Logic Control

Logic PT Single PT for XOR/OR

+1 Logic PT Individual Clock (PT Clock)

+2 Logic PT Individual Initialization or Individual Clock Enable (PT Initialization/CE)

+3 Logic PT Individual Initialization (PT Initialization)

+4 Logic PT Individual OE (PTOE)

Macrocell Available Clusters

M0 — C0C1C2

M1 C0 C1 C2 C3

M2 C1 C2 C3 C4

M3 C2 C3 C4 C5

M4 C3 C4 C5 C6

M5 C4 C5 C6 C7

M6 C5 C6 C7 C8

M7 C6 C7 C8 C9

M8 C7 C8 C9 C10

M9 C8 C9 C10 C11

M10 C9 C10 C11 C12

M11 C10 C11 C12 C13

M12 C11 C12 C13 C14

M13 C12 C13 C14 C15

M14 C13 C14 C15 —

M15 C14 C15 — —

Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet

Table 5. Product Term Expansion Capability

Every time the super cluster allocator is used, there is an incremental delay of t

EXP

. When the super cluster alloca-

tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-

ter is steered to M (n+4), then M (n) is ground).

Macrocell

The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-

grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.

Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input

from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable

delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.

Figure 5. Macrocell

Enhanced Clock Multiplexer

The clock input to the ﬂip-ﬂop can select any of the four block clocks along with the shared PT clock, and true and

complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The

eight sources for the clock multiplexer are as follows:

• Block CLK0

• Block CLK1

• Block CLK2

Expansion Chains Macrocells Associated with Expansion Chain (with Wrap Around) Max PT/Macrocell

Chain-0 M0

→

M12

→

M0 75

Chain-1 M1

→

M13

→

M1 80

Chain-2 M2

→

M10

→

M14

→

M2 75

Chain-3 M3

→

M11

→

M15

→

M3 70

Single PT

Block CLK0

Block CLK1

Block CLK2

Block CLK3

PT Clock (optional)

Shared PT Clock

D/T/L Q

Shared PT Initialization

PT Initialization/CE (optional)

PT Initialization (optional)

From Logic Allocator

Power-up

Initialization

To ORP

To GRP

From I/O Cell

Delay

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

LA4032V-75TN44E

Mfr. #:

Buy LA4032V-75TN44E

Manufacturer:

Lattice

Description:

CPLD - Complex Programmable Logic Devices Auto Grade (AEC-Q100 ) ispMACH4032V

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LA4032V-75TN44E

LA4032V-75TN44E

Products related to this Datasheet