PDF: 09005aef8082c948/Source: 09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddf9c32_64x72.fm - Rev. C 10/08 EN
7 ©2002 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
General Description
General Description
The MT9VDDF3272 and MT9VDDF6472 are high-speed, CMOS dynamic random access
256MB and 512MB memory modules organized in a x72 configuration. These DDR
SDRAM modules use internally configured four-bank (256Mb or 512Mb) DDR SDRAM
devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single read
or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-
clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Register and PLL Operation
These DDR SDRAM modules operate in registered mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by one
clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential
clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce
control, command, address, and clock signals loading by isolating DRAM from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various DDR SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard I
2
C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to V
SS,
permanently disabling hardware write protect.
