DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
15
APPLICATIONS (CONT'D)
Power Supplies and Decoupling
A useful feature of the DG534A/538A is its power supply
flexibility. It can be operated from unipolar supplies (V–
connected to 0 V) if required. Allowable operating voltage
ranges are shown in Figure 13.
Note that the analog signal must not go below V– by more than
0.3 V (see absolute maximum ratings). However, the addition
of a V– pin has a number of advantages:
a. It allows flexibility in analog signal handling, i.e. with V– =
–5 V and V+ = 15 V, up to "5 V ac signals can be
accepted.
b. The value of on capacitance (C
S(on)
) may be reduced by
increasing the reverse bias across the internal FET body to
source junction. V+ has no effect on C
S(on)
.
It is useful to note that tests indicate that optimum video
differential phase and gain occur when V– is –3 V.
c. V– eliminates the need to bias an ac analog signal using
potential dividers and large decoupling capacitors.
It is established rf design practice to incorporate sufficient
bypass capacitors in the circuit to decouple the power supplies
to all active devices in the circuit. The dynamic performance
of the DG534/538 is adversely affected by poor decoupling of
power supply pins. Also, since the substrate of the device is
connected to the negative supply, proper decoupling of this pin
is essential.
Rules:
a. Decoupling capacitors should be incorporated on all
power supply pins (V+, V–, V
L
).
b. They should be mounted as close as possible to the
device pins.
c. Capacitors should have good frequency characteristics -
tantalum bead and/or ceramic disc types are suitable.
Recommended decoupling capacitors are 1- to 10-F
tantalum bead, in parallel with 100-nF ceramic or
polyester.
d. Additional high frequency protection may be provided by
51- carbon film resistors connected in series with the
power supply pins (see Figure 14).
Board Layout
PCB layout rules for good high frequency performance must
also be observed to achieve the performance boasted by the
DG534A/538A. Some tips for minimizing stray effects are:
a. Use extensive ground planes on double sided PCB
separating adjacent signal paths. Multilayer PCB is even
better.
b. Keep signal paths as short as practically possible with all
channel paths of near equal length.
c. Use strip-line layout techniques.
Improvements in performance can be obtained by using PLCC
parts instead of DIPs. The stray effects of the quad PLCC
package are lower than those of the dual-in-line packages.
Sockets for the PLCC packages usually increase crosstalk.
DG534A
+5 V +15 V
–3 V
+
++
V–
V+
GND
S
A1
S
A2
S
B1
S
B2
D
A
D
B
C
2
C
1
C
1
C
2
51 W
51
51
C
1
C
2
C
1
= 1 F Tantalum
C
2
= 100 nF Polyester
FIGURE 14. DG534A Power Supply Decoupling
V
L
Interfacing
Logic interfacing is easily accomplished. Comprehensive
addressing and control functions are incorporated in the
design.
The V
L
pin permits interface to various logic types. The device
is primarily designed to be TTL or CMOS logic compatible with
+5 V applied to V
L
. The actual logic threshold can be raised
simply by increasing V
L
.
