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LSM2-T/6-W3-C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
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LSM2 Series
Single Output, Non-Isolated
Selectable-Output POL DC/DC Converters
MDC_LSM2 Series.D01∆ Page 13 of 17
Power Phasing Architectures
Observe the simplified timing diagrams below. There are many possible power
phasing architectures and these are just some examples to help you analyze
your system. Each application will be different. Multiple output voltages may
require more complex timing than that shown here.
These diagrams illustrate the time and slew rate relationship between two
typical power output voltages. Generally the Master will be a primary power
voltage in the system which must be present first or coincident with any
Slave power voltages. The Master output voltage is connected to the Slave’s
Sequence input, either by a voltage divider, divider-plus-capacitor or some
other method. Several standard sequencing architectures are prevalent. They
are concerned with three factors:
The time relationship between the Master and Slave voltages
The voltage difference relationship between the Master and Slave
The voltage slew rate (ramp slope) of each converter’s output.
For most systems, the time relationship is the dominant factor. The voltage
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew rates
avoid overcurrent shutdown during bypass cap charge-up.
In Figure 10, two POL’s ramp up at the same rate until they reach their
different respective final set point voltages. During the ramp, their voltages
are nearly identical. This avoids problems with large currents flowing between
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
Figures 12 and 13 show both delayed start up and delayed final voltages
for two converters. Figure 12 is called “Inclusive” because the later starting
POL finishes inside the earlier POL. The timing in Figure 12 is more easily built
using a combined digital sequence controller and the Sequence/Track pin.
Figure 13 is the same strategy as Figure 12 but with an “exclusive” timing
relationship staggered approximately the same at power-up and power-down.
POL A V
OUT
TIME
OUTPUT
VOLTAGE
POL B V
OUT
Coincident
V
OUT
Times
Figure 11. Proportional or Ratiometric Phasing (Identical VOUT Time)
+V
OUT
POL A V
OUT
TIME
OUTPUT
VOLTAGE
POL B V
OUT
Staggered
Times
Figure 10. Coincident or Simultaneous Phasing (Identical Slew Rates)
POL A V
OUT
TIME
OUTPUT
VOLTAGE
POL B V
OUT
Delayed
V
OUT
Times
POL A V
OUT
TIME
OUTPUT
VOLTAGE
POL B V
OUT
Delayed
V
OUT
Times
Not Drawn To Scale
Figure 12. Staggered or Sequential Phasing—Inclusive (Fixed Delays)
Figure 13. Staggered or Sequential Phasing—Exclusive
(Fixed Cascaded Delays)
Figure 11 shows two POL’s with different slew rates in order to reach differ-
ing final voltages at about the same time.
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LSM2 Series
Single Output, Non-Isolated
Selectable-Output POL DC/DC Converters
MDC_LSM2 Series.D01∆ Page 14 of 17
POL A
+V
IN
+V
OUT
= 5V
–V
IN
SEQ/TRK
UP/DN
R1
Q1
C1
Figure 15. Self-Ramping Power Up
Operation
To use the Sequence pin after power start-up stabilizes, apply a rising external
voltage to the Sequence input. As the voltage rises, the output voltage will
track the Sequence input (gain = 1). The output voltage will stop rising when it
reaches the normal set point for the converter. The Sequence input may option-
ally continue to rise without any effect on the output. Keep the Sequence input
voltage below the converter’s input supply voltage.
Use a similar strategy on power down. The output voltage will stay constant
until the Sequence input falls below the set point.
Any strategy may be used to deliver the power up/down ramps. The circuits
below show simple RC networks but you may also use operational amplifiers,
D/A converters, etc.
Circuits
The circuits shown in Figures 14 through 16 introduce several concepts when
using these Sequencing controls on Point-of-Load (POL) converters. These
circuits are only for reference and are not intended as final designs ready for
your application. Also, numerous connections are omitted for clarity.
Figure 15 shows a single POL and the same RC network. However, we have
added a FET at Q1 as an up/down control. When VIN power is applied to the
POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased
off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate. Note:
Q1’s gate would typically be controlled from some external digital logic.
POL A
POL B
+V
IN
+V
OUT
= 5V
+V
OUT
= 3.3V
–V
IN
SEQ/TRK
SEQ/TRK
R1
C1
Figure 14. Wiring for Simultaneous Phasing
POL A
POL B
+V
IN
+V
OUT
= 5V
+V
OUT
= 3.3V
–V
IN
–V
IN
SEQ/TRK
SEQ/TRK
ANTI-NOISE FILTER, 1000pF TYP.
MAIN
RAMP
RATE
R1
C1
C2
R3
R2
Figure 16. Proportional Phasing
Figure 14 shows a basic Master (POL A) and Slave (POL B) connected so the
POL B ramps up identically to POL A as shown in timing diagram, Figure 10. RC
network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving
a roughly linear ramp. As POL A reaches 3.3VOUT (the setpoint of POL B), POL
B will stop rising. POL A then continues rising until it reaches 5V. R1 should be
significantly smaller than the internal bias current resistor from the Sequence
pin. Start with a 20kW value. We assume that the critical phase is only on
power up therefore there is no provision for ramped power down.
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q1’s drain.
Figure 16 shows both a RC ramp on Master POL A and a proportional track-
ing divider (R2 and R3) on POL B. We have also added an optional very small
noise filter cap at C2. Figure 16’s circuit corresponds roughly to Figure 11’s
timing for power up.
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[8] If one converter is slaving to another master converter, there will be a very
short phase lag between the two converters. This can usually be ignored.
[9] You may connect two or more Sequence inputs in parallel from two con-
verters. Be aware of the increasing pull-up bias current and reduced input
impedance.
[10] Any external capacitance added to the converter’s output may affect ramp
up/down times and ramp tracking accuracy.
Power Good Output
The Power Good Output consists of an unterminated BSS138 small signal
field effect transistor and a dual window comparator input circuit driving the
gate of the FET. Power Good is TRUE (open drain, high impedance state) if the
converter’s power output voltage is within about ±10% of the setpoint. Thus,
the PG TRUE condition indicates that the converter is approximately within
regulation. Since an overcurrent condition occurs at about 2% output voltage
reduction, the Power Good does not directly measure an output overcurrent
condition at rated maximum output current. However, gross overcurrent or an
output short circuit will set Power Good to FALSE (+0.2V saturation, low imped-
ance condition).
BSS138
HI
LO
10mA
MAX.
Window
Comparator
External Pullup
Resistor
POWER
GOOD
POWER
OUTPUT
HI (Open Drain) = Power OK
LO (+0.2V Saturation) = Power not OK
LOGIC
GROUND
+LOGIC
SUPPLY
COMMON
User’s External
Logic
Figure 18. Equivalent Power Good Circuit
Using a simple connection to external logic (and returned to the converter’s
Common connection), the Power Good output is unterminated so that the user
may adapt the output to a variety of logic families. The PG pin may therefore
be used with logic voltages which are not necessarily the same as the input
or output power voltages. Install an external pullup resistor to the logic supply
voltage which is compatible with your logic system. When the Power Good is
out of limit, the FET is at saturation, approximately +0.2V output. Keep this
LOW (FALSE) pulldown current to less than 10mA.
Please note that Power Good is briefly false during Sequence ramp-up.
Ignore Power Good while in transition.
LSM2 Series
Single Output, Non-Isolated
Selectable-Output POL DC/DC Converters
MDC_LSM2 Series.D01∆ Page 15 of 17
Guidelines for Sequence/Track Applications
[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.
Normally, you should just leave the On/Off pin open.
[2] Allow the converter to stabilize (typically less than 20 mS after +VIN power
on) before raising the Sequence input. Also, if you wish to have a ramped
power down, leave +VIN powered all during the down ramp. Do not simply
shut off power.
[3] If you do not use the Sequence/Track pin, leave it open or tied to +VIN.
[4] Observe the Output slew rate relative to the Sequence input. A rough
guide is 2 Volts per millisecond maximum slew rate. If you exceed this
slew rate on the Sequence pin, the converter will simply ramp up at
it’s maximum output slew rate (and will not necessarily track the faster
Sequence input). The reason to carefully consider the slew rate limitation
is in case you want two different POL’s to precisely track each other.
[5] Be aware of the input characteristics of the Sequence pin. The high input
impedance affects the time constant of any small external ramp capacitor.
And the bias current will slowly charge up any external caps over time
if they are not grounded. The internal pull-up resistor to +VIN is typically
400kW to 1MW.
Notice in the simplified Sequence/Track equivalent circuit (Figure 17) that
a blocking diode effectively disconnects this circuit when the Sequence/
Track pin is pulled up to +VIN or left open.
+V
IN
+V
OUT
+V
IN
+
–
1MΩ
TRIM
FEEDBACK
SEQ/
TRK
IN
PWM
CONTROLLER
Figure 17. Sequence/Track Simplified Equivalent Schematic
[6] Allow the converter to eventually achieve its full-rated setpoint output
voltage. Do not remain in ramp up/down mode indefinitely. The converter
is characterized and meets all its specifications only at the setpoint volt-
age (plus or minus any trim voltage). During the ramp-up phase, the con-
verter is not considered fully in regulation. This may affect performance
with excessive high current loads at turn-on.
[7] The Sequence is a sensitive input into the feedback control loop of the
converter. Avoid noise and long leads on this input. Keep all wiring very
short. Use shielding if necessary. Consider adding a small parallel ceramic
capacitor across the Sequence/Track input (see Figure 16) to block any
external high frequency noise.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

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