NCP81245
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22
VSP
CSP
CSN
RPHSP
RCSSP
t
Rth
CCSSP
TO
RDRPSP
CDRPSP
CSNSSP
TO
VCC_SENSE
CURRENT
SENSE AMP
VSN
VSP
_
+
Av=1
gm
Figure 18.
V
DROOP
+ R
DRPSP
gm
Rth ) R
CSSP
R
PHSP
) Rth ) R
CSSP
I
OUT
DCR
The loadline is programmed by choosing R
DRPSP
such
that the ratio of voltage produced across R
DRPSP
to output
current is equal to the desired loadline.
R
DRPSP
+
Loadline
gm DCR
R
PHSP
) Rth ) R
CSSP
Rth ) R
CSSP
(eq. 17)
Single−phase Rail − Programming the DAC
Feed−Forward Filter
The DAC feed−forward implementation for the
single−phase rail is the same as for the multi−phase rails. The
NCP81245 outputs a pulse of current from the VSN pin upon
each increment of the internal DAC following a DVID UP
command. A parallel RC network inserted into the path from
VSN to the output voltage return sense point, VSS_SENSE,
causes these current pulses to temporarily decrease the
voltage between VSP and VSN. This causes the output
voltage during DVID to be regulated slightly higher, in order
to compensate for the response of the Droop function to the
inductor current flowing into the charging output capacitors.
RFFSP sets the gain of the DAC feed−forward and CFFSP
provides the time constant to cancel the time constant of the
system per the following equations. Cout is the total output
capacitance of the system.
VSP
VSN
RFFSP
CFFSP
CSNSSP
TO
VSS_SENSE
DAC
DAC
FORWARD
VSN
VSP
DAC
FEED−
DAC FEEDFORWARD
CURRENT
FROM SVID
INTERFACE
gm
Figure 19.
R
FFSP
+
Loadline * Cout
1.35 nF
(eq. 18)
C
FFSP
+
200 ns
R
FFSP
(eq. 19)
Single−phase Rail − Programming the Current Limit
The current limit threshold is programmed with a resistor
(R
ILIMSP
) from the ILIM pin to ground. The current limit
latches the single−phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold. Set the value of the
current limit resistor based on the equation shown below. A
capacitor can be placed in parallel with the programming
resistor to slightly delay activation of the latch if some
tolerance of short overcurrent events is desired.
NCP81245
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23
CSP
CSN
ILIM
RPHSP
RCSSP
t
Rth
CCSSP
INDUCTOR
TO
RILIMSP
PROGRAMMING
COMPARATORS
OVERCURRENT
OVERCURRENT
CURRENT
SENSE AMP
OCP
OCP REF
_
+
Av=1
gm
Figure 20.
R
ILIMSP
+
1.3 V
gm @
Rth)R
CSSP
R
PHSP
)Rth)R
CSSP
Iout
LIMIT
DCR
When selecting the current limit it is necessary to take into
account the additional inductor current due to the slew rate
of the output voltage across the output capacitance during
VID changes, as this excess current may cause the OCP limit
to be exceeded. This excess current is given by:
I + Cout
dVout
dt
(eq. 20)
where
dVout
dt
is the maximum slew rate
Single−phase Rail − Programming IOUT
The IOUT pin sources a current in proportion to the
ILIMIT sink current. The voltage on the IOUT pin is
monitored by the internal A/D converter and should be
scaled with an external resistor to ground such that a load
equal to ICCMAX generates a 2 V signal on IOUT. A
pull−up resistor from 5 V V
CC
can be used to offset the
IOUT signal positive if needed.
CSP
CSN
IOUT
RPHSP
RCSSP
t
Rth
CCSSP
INDUCTOR
TO
RIOUTSP
MONITOR
CURRENT
CURRENT
SENSE AMP
IOUT
_
+
Av=1
gm
Figure 21.
R
IOUTSP
+
2V
gm
Rth)R
CSSP
R
PHSP
)Rth)R
CSSP
IccMax DCR
Single−phase Rail PWM Comparators
The non−inverting input of each comparator (one for each
phase) is connected to the summation of the output of the
error amplifier (COMP) and each phase current
(I
L
*DCR*Phase Current Gain Factor). The inverting input
is connected to the triangle ramp voltage of that phase. The
output of the comparator generates the PWM output.
A PWM pulse starts when the error amp signal (COMP
voltage) rises above the trigger threshold plus gained−up
inductor current, and stops when the artificial ramp plus
gained−up inductor current crosses the COMP voltage. Both
edges of the PWM signals are modulated. During a transient
event, the duty cycle can increase rapidly as the COMP
voltage increases with respect to the ramps, to provide a
highly linear and proportional response to the step load.
Programming ICC_MAX (single phase)
A resistor to ground on the IMAX pin programs these
registers at the time the part is enabled. 10 mA is sourced
from these pins to generate a voltage on the program resistor.
The resistor value should be no less than 10k.
ICC_MAX
21h
+
Rmax* 10 mA * 256 A
4*2V
(eq. 21)
NCP81245
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24
PACKAGE DIMENSIONS
QFN52 6x6, 0.4P
CASE 485BE
ISSUE B
SEATING
NOTE 4
K
0.10 C
(A3)
A
A1
D2
b
1
14
27
52
E2
52X
L
BOTTOM VIEW
DETAIL C
TOP VIEW
SIDE VIEW
D
A B
E
0.10
C
PIN ONE
LOCATION
0.10 C
0.08 C
C
40
e
A0.07 BC
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.15 0.25
D 6.00 BSC
D2 4.60 4.80
E 6.00 BSC
4.80E2 4.60
e 0.40 BSC
L 0.25 0.45
L1 0.00 0.15
NOTE 3
PLANE
DIMENSIONS: MILLIMETERS
0.25
4.80
0.40
4.80
52X
0.63
52X
6.40
6.40
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DETAIL B
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
K 0.30 REF
PITCH
52X
PKG
OUTLINE
L2 0.15 REF
L2
DETAIL C
8 PLACES
L2
DETAIL A
DETAIL D
8 PLACES
0.11
0.49
DETAIL D
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NCP81245MNTXG

Mfr. #:
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ON Semiconductor
Description:
Switching Controllers IMVP8 3+2+1 SVID CONTRO
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