NCP81245
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Table 1. QFN52 PIN LIST DESCRIPTION
Pin DescriptionName
38 VSP_3PH_B Differential output voltage sense positive for multi−phase rail “B”
39 VR_HOT# Thermal logic output for over−temperature condition on TTSENSE pins
40 SDIO Serial VID data interface
41 ALERT# Serial VID ALERT#
42 SCLK Serial VID clock
43 EN Enable input. High enables all three rails
44 PWM_1PH /
ICCMAX_1PH
PWM output of the single−phase rail /
A resistor to ground programs ICCMAX for the single−phase rail
45 VR_RDY VR_RDY indicates all three rails are ready to accept Intel proprietary interface commands
46 IMON_1PH A resistor to ground programs IOUT gain for the single−phase rail
47 CSP_1PH Differential current sense positive for the single−phase rail
48 CSN_1ph Differential current sense negative for the single−phase rail
49 ILIM_1ph A resistor to ground programs ILIM gain for the single−phase rail
50 COMP_1ph Compensation for single−phase rail
51 VSN_1ph Differential output voltage sense negative for single−phase rail
52 VSP_1ph Differential output voltage sense positive for single−phase rail
53 Tab GND
ELECTRICAL INFORMATION
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol V
MAX
V
MIN
I
SOURCE
I
SINK
COMPX VCC + 0.3 V −0.3 V 2 mA 2 mA
CSCOMPX VCC + 0.3 V −0.3 V 2 mA 2 mA
VSN GND + 300 mV GND−300 mV 1 mA 1 mA
VRDY VCC + 0.3 V −0.3 V N/A 2 mA
VCC 6.5 V −0.3 V N/A N/A
VRMP +25 V −0.3 V
All Other Pins VCC + 0.3 V −0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*All signals referenced to GND unless noted otherwise.
Table 3. THERMAL INFORMATION
Description Symbol Typ Unit
Thermal Characteristic
QFN Package (Note 1)
R
JA
68 °C/W
Operating Junction Temperature Range (Note 2) T
J
−40 to +125 °C
Operating Ambient Temperature Range −40 to +100 °C
Maximum Storage Temperature Range T
STG
−40 to +150 °C
Moisture Sensitivity Level
QFN Package
MSL 1
*The maximum package power dissipation must be observed.
1. 2) JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. 3) JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40
°
C < T
A
< 100
°
C; 4.75 V < V
CC
< 5.25 V ; C
VCC
= 0.1mF
Parameter
Test Conditions Min Typ Max Unit
ERROR AMPLIFIER
Input Bias Current
−900 900 nA
Open Loop DC Gain CL = 20 pF to GND,
RL = 10 kW to GND
80 dB
Open Loop Unity Gain Bandwidth CL = 20 pF to GND,
RL = 10 kW to GND
20 MHz
Slew Rate
DVin = 100 mV, G = −10 V/V,
DVout = 0.75 V − 1.52 V,
CL = 20 pF to GND,
DC Load = 10k to GND
5
V/ms
Maximum Output Voltage I
SOURCE
= 2.0 mA 3.5 V
Minimum Output Voltage I
SINK
= 2.0 mA 1 V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
−25 25 nA
VSP Input Voltage Range −0.3 3.0 V
VSN Input Voltage Range −0.3 0.3 V
−3dB Bandwidth CL = 20 pF to GND,
RL = 10 k W to GND
22.5 MHz
Closed Loop DC gain
VS to DIFF
VS+ to VS− = 0.5 to 1.3 V 1.0 V/V
Maximum Output Voltage I
SOURCE
= 2 mA 3.5 V
Minimum Output Voltage I
SINK
= 2 mA 0.8 V
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
−300 300
mV
Input Bias Current CSREF= 1 V −7.5 7.5
mA
Input Bias Current CSSUM= 1 V −7.5 7.5 nA
Open Loop Gain 80 dB
Current Sense Unity Gain Bandwidth C
L
= 20 pF to GND,
R
L
= 10 kW to GND
15 MHz
Maximum CSCOMP (A) Output Voltage Isource = 2 mA 3.5 V
Minimum CSCOMP(A) Output Voltage Isink = 500 uA 0.15 V
CURRENT BALANCE AMPLIFIER
Input Bias Current
CSPX − CSPX + 1 = 1.2 V −50 50 nA
Common Mode Input Voltage Range CSPx = CSREF 0 2.3 V
Differential Mode Input Voltage Range CSNx = 1.2 V −100 100 mV
Closed loop Input Offset Voltage Matching CSPx = 1.2 V,
Measured from the average
−1.5 1.5 mV
Current Sense Amplifier Gain 0V < CSPx < 0.1 V, 5.7 6.0 6.3 V/V
Multiphase Current Sense Gain Matching CSREF = CSP = 10 mV to 30 mV −3 3 %
−3dB Bandwidth 8 MHz
BIAS SUPPLY
Supply Voltage Range
4.75 5.25 V
VCC Quiescent Current Enable high 33 50 mA
VCC Quiescent Current Enable low 60
mA
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Table 4. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40
°
C < T
A
< 100
°
C; 4.75 V < V
CC
< 5.25 V ; C
VCC
= 0.1mF
Parameter UnitMaxTypMinTest Conditions
BIAS SUPPLY
UVLO Threshold
VCC rising 4.5
V
VCC falling 4
VCC UVLO Hysteresis 250 mV
VRMP
Supply Range
4.5 20 V
UVLO Threshold
VRamp rising 4.25 V
VRamp falling 3 V
UVLO Hysteresis 675 mV
DAC SLEW RATE
Slew Rate Fast
>10
mV/ms
Soft Start Slew Rate 1/2 SR
Fast
mV/ms
Slew Rate Slow 1/2 SR
Fast
mV/ms
ENABLE INPUT
Enable High Input Leakage Current
Enable = 0 −1 1
mA
V
IH
0.8 V
V
IL
0.3 V
Enable Delay Time Measure time from Enable tran-
sitioning HI , VBOOT is not 0 V
2.5 ms
DRON
Output High Voltage
Sourcing 500 mA
3.0 V
Output Low Voltage
Sinking 500 mA
0.1 V
Pull Up Resistances 2.0
kW
Rise/Fall Time CL (PCB) = 20 pF,
DVo = 10% to 90%
160 ns
Internal Pull Down Resistance V
CC
= 0 V 70
kW
OVERCURRENT PROTECTION
Ilim Threshold Current
(delayed OCP shutdown)
PS0 9 10 11 mA
PS1, PS2, PS3
(N = PS0 phase count)
10/N
Ilim Threshold Current
(immediate OCP shutdown)
PS0 13.5 15 16.5 mA
PS1, PS2, PS3
(N = PS0 phase count)
15/N
Shutdown Delay
Immediate 300 ns
Delayed 50
ms
ILIM Output Voltage Offset
Ilim sourcing 10 mA
−2 2 mV
IOUT_3PH_A/IOUT_3PH_B OUTPUT
Output Offset Current
V
Ilim
= 5 V 0.25
mA
Output current max
Ilimit sink current 20 mA
200
mA
Current Gain (Iout current)/(Ilimit Current)
Rlim = 20k, Riout = 5k
DAC = 0.8 V, 1.25 V, 1.52 V
9.5 10 10.5 A/A

NCP81245MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers IMVP8 3+2+1 SVID CONTRO
Lifecycle:
New from this manufacturer.
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