TJA1086G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 13 July 2017 22 of 64
NXP Semiconductors
TJA1086G
FlexRay active star coupler)
The assignment of control and status register addresses is detailed in Table 7. Data can
only be written to the Control and Configuration registers (status registers are read-only
by definition). Therefore the state of bit 12 is only evaluated when these registers are
being accessed.
[1] Bit 12 is assumed to be 1 for status registers
The following subsections provide details of the bits in these registers and the control and
status functionality assigned to each.
Table 7. Register map
Address bits 15, 14 and 13 Write access bit 12
[1]
Register
000 0 =R/W, 1 = R/O Control register; see Table 8
001 1 = R/O Interrupt status register; see Table 10
010 1 = R/O General status register; see Table 11
011 1 = R/O Branch 1 status register; see Table 12
100 1 = R/O Branch 2 status register; see Table 12
111 0 =R/W, 1 = R/O Configuration register; see Table 9
TJA1086G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 13 July 2017 23 of 64
NXP Semiconductors
TJA1086G
FlexRay active star coupler)
7.10.2.1 Control register
The read/write Control register allows the host controller to set the operating modes and
to switch the TJA1086G between HC and AP modes.
[1] The TJA1086G sets the APM flag at power-on, in response to a wake-up event (local, remote or TRXD), if
a V
CC
undervoltage is detected in AS_Normal or a V
IO
undervoltage is detected for longer than t
to(uvd)(VIO)
.
[2] Setting the RESET_ERROR bit resets all error status bits in the General Status (bits 8 to 1) and Branch
Status registers (bits 7 to 4).
Table 8. Control register bit description
Bit Symbol Access Default Description
11:10 OPM R/W 00 operating mode:
00: no change
01: AS_Standby
10: AS_Sleep
11: AS_Normal
9:8 CTRL_BR1 R/W 00 branch 1 control:
00: no change
01: Branch_Normal
10: Branch_TxOnly
11: Branch_Disabled
7:6 CTRL_BR2 R/W 00 branch 2 control:
00: no change
01: Branch_Normal
10: Branch_TxOnly
11: Branch_Disabled
5:2 reserved after power-up, write 1111 once to bits [5:2] in
AS_Standby before entering AS_Normal to
minimize the power supply current
1 APM
[1]
R/W 1 Autonomous Power mode
0: disabled
1: enabled
0 RESET_ERROR
[2]
R/W 0 reset error flags and status bits
0: no change
1: reset flags/bits
TJA1086G All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 13 July 2017 24 of 64
NXP Semiconductors
TJA1086G
FlexRay active star coupler)
7.10.2.2 Configuration register
The read/write Configuration register allows the host controller to configure a number of
TJA1086G parameters and functions.
Table 9. Configuration register bit description
Bit Symbol Access Default Description
11 AEC R/W 0 Autonomous error confinement:
0: disabled
1: enabled
10 BFT R/W 1 Bus failure timer
0: disabled
1: enabled
9 WUD_BR1 R/W 1 wake-up detection on branch 1:
0: disabled
1: enabled
8 WUD_BR2 R/W 1 wake-up detection on branch 2:
0: disabled
1: enabled
7:6 reserved after power-up, write 00 once to bits [7:6] to
minimize the power supply current
5 CC_EN R/W 0 CC interface enable (TXD and TXEN inputs;
RXD output):
0: disabled
1: enabled
4 TRXD_EN R/W 1 TRXD interface enable:
0: disabled
1: enabled
3 reserved always 0
2 CLAMP_DET R/W 1 clamping detection:
0: disabled
1: enabled
1 BIT_LATCHING R/W 0 status bit latching:
0: disabled
1: enabled
0 PARITY R - parity bit - odd parity (including parity bit)

TJA1086GHN/0Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized TJA1086GHN/HVQFN44//0/REEL 13 Q1 NDP SSB
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