AD7895BRZ-10 Datasheet AD7895ARZ-10REEL, AD7895ANZ-2, AD7895ARZ-10 | P10-P12

AD7895

–9–

REV. 0

MICROPROCESSOR/MICROCONTROLLER INTERFACE

The AD7895 provides a three-wire serial interface that can be

used for connection to the serial ports of DSP processors and

microcontrollers. Figures 6 through 9 show the AD7895

interfaced to a number of different microcontrollers and DSP

processors. The AD7895 accepts an external serial clock, and

as a result, in all interfaces shown here, the processor/controller

is configured as the master, providing the serial clock with the

AD7895 configured as the slave in the system.

AD7895–8051 Interface

Figure 6 shows an interface between the AD7895 and the 8XL51

microcontroller. The 8XL51 is configured for its Mode 0 serial

interface mode. The diagram shows the simplest form of the

interface where the AD7895 is the only part connected to the

serial port of the 8XL51 and, therefore, no decoding of the

serial read operations is required.

AD7895

SDATA

SCLK

BUSY

P3.0

P3.1

8X51/L51

P1.2

INT1

Figure 6. AD7895 to 8X51/L51 Interface

To chip select the AD7895 in systems where more than one

device is connected to the 8XL51’s serial port, a port bit

configured as an output, from one of the 8XL51’s parallel ports

can be used to gate on or off the serial clock to the AD7895. A

simple AND function on this port bit and the serial clock from

the 8XL51 will provide this function. The port bit should be

high to select the AD7895 and low when it is not selected.

The end of conversion is monitored by using the BUSY signal

that is shown in the interface diagram of Figure 6. The BUSY

line from the AD7895 is connected to the Port P1.2 of the

8XL51 so the BUSY line can be polled by the 8XL51. The BUSY

line can be connected to the INT1 line of the 8XL51 if an

interrupt driven system is preferred. These two options are

shown in the diagram.

Note also that the AD7895 outputs the MSB first during a read

operation, while the 8XL51 expects the LSB first. Therefore,

the data which is read into the serial buffer needs to be rear-

ranged before the correct data format from the AD7895 appears

in the accumulator.

The serial clock rate from the 8XL51 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7895 can operate. As a result, the time to read data

from the part will actually be longer than the conversion time of

the part. This means that the AD7895 cannot run at its maximum

throughput rate when used with the 8XL51.

AD7895–68HC11/L11 Interface

An interface circuit between the AD7895 and the 68HC11/L11

microcontroller is shown in Figure 7. For the interface shown,

the 68L11 SPI port is used, and the 68L11 is configured in its

single-chip mode. The 68L11 is configured in the master mode

with its CPOL bit set to a logic zero and its CPHA bit set to a

logic one. As with the previous interface, the diagram shows the

simplest form of the interface where the AD7895 is the only part

connected to the serial port of the 68L11 and, therefore, no

decoding of the serial read operations is required.

AD7895

SDATA

SCLK

BUSY

SCK

MISO

68HC11/L11

PC2 OR

IRQ

Figure 7. AD7895 to 68HC11/L11 Interface

Once again, to chip select the AD7895 in systems where more

than one device is connected to the 68HC11’s serial port, a port

bit configured as an output from one of the 68HC11’s parallel

ports can be used to gate on or off the serial clock to the

AD7895. A simple AND function on this port bit and the serial

clock from the 68L11 will provide this function. The port bit

should be high to select the AD7895 and low when it is not

selected.

The end of conversion is monitored by using the BUSY signal

that is shown in the interface diagram of Figure 7. With the

BUSY line from the AD7895 connected to the Port PC0 of the

68HC11/L11, the BUSY line can be polled by the 68HC11/L11.

The BUSY line can be connected to the

IRQ line of the

68HC11/L11 if an interrupt driven system is preferred. These

two options are shown in the diagram.

The serial clock rate from the 68HC11/L11 is limited to

significantly less than the allowable input serial clock frequency

with which the AD7895 can operate. As a result, the time to

read data from the part will actually be longer than the conver-

sion time of the part. This means that the AD7895 cannot run

at its maximum throughput rate when used with the 68HC11/L11.

AD7895–ADSP-2103/5 Interface

An interface circuit between the AD7895 and the ADSP-2103/5

DSP processor is shown in Figure 8. In the interface shown, the

RFS1 output from the ADSP-2103/5s SPORT1 serial port is

used to gate the serial clock (SCLK1) of the ADSP-2103/5

before it is applied to the SCLK input of the AD7895. The

RFS1 output is configured for active high operation. The BUSY

line from the AD7895 is connected to the

IRQ2 line of the

ADSP-2103/5 so that at the end of conversion an interrupt is

generated telling the ADSP-2103/5 to initiate a read operation.

The interface ensures a noncontinuous clock for the AD7895’s

serial clock input with only sixteen serial clock pulses provided

and the serial clock line of the AD7895 remaining low between

data transfers. The SDATA line from the AD7895 is connected

to the DR1 line of the ADSP-2103/5’s serial port.

AD7895

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REV. 0

AD7895

SDATA

SCLK

BUSY

SCLK1

DR1

ADSP-2103/5

IRQ2

RFS1

Figure 8. AD7896 to ADSP-2103 /5 Interface

The timing relationship between the SCLK1 and RFS1 outputs

of the ADSP-2103/5 are such that the delay between the rising

edge of the SCLK1 and the rising edge of an active high RFS1

is up to 30 ns. There is also a requirement that data must be

set up 10 ns prior to the falling edge of the SCLK1 to be read

correctly by the ADSP-2103/5. The data access time for the

AD7895 is 60 ns (5 V (A, B versions)) from the rising edge of

its SCLK input. Assuming a 10 ns propagation delay through

the external AND gate, the high time of the SCLK1 output of

the ADSP-2105 must be ≥ (30 + 60 +10 +10) ns, i.e., ≥ 110 ns.

This means that the serial clock frequency with which the

interface of Figure 8 can work is limited to 4.5 MHz. However,

there is an alternative method that allows for the ADSP-2105

SCLK1 to run at 5 MHz (the max serial clock frequency of the

SCLK1 output). The arrangement occurs when the first leading

zero of the data stream from the AD7895 cannot be guaranteed

to be clocked into the ADSP-2105 due to the combined delay of

the RFS signal and the data access time of the AD7895. In most

cases, this is acceptable because there will still be three leading

zeros followed by the 12 data bits. For the ADSP-2103, the

SCLK1 frequency will need to be limited to < 4 MHz to

account for the 100 ns data access time of the AD7895.

Another alternative scheme is to configure the ADSP-2103/5 so

that it accepts an external noncontinuous serial clock. In this

case, an external noncontinuous serial clock is provided that

drives the serial clock inputs of both the ADSP-2103/5 and the

AD7895. In this scheme, the serial clock frequency is limited to

15 MHz by the AD7895.

AD7895–DSP56002/L002 Interface

Figure 9 shows an interface circuit between the AD7895 and the

DSP56002/L002 DSP processor. The DSP56002/L002 is

configured for normal mode asynchronous operation with gated

clock. It is also set up for a 16-bit word with SCK as gated

clock output. In this mode, the DSP56002/L002 provides

sixteen serial clock pulses to the AD7895 in a serial read

operation. Because the DSP56002/L002 assumes valid data on

the first falling edge of SCK, the interface is simply two-wire as

shown in Figure 9.

AD7895

SDATA

SCLK

BUSY

SCK

SDR

DSP56002/L002

MODA / IRQA

Figure 9. AD7895 to DSP56002/L002 Interface

Because the BUSY line from the AD7895 is connected to the

MODA/

IRQA input of the DSP56002/L002, an interrupt will

be generated at the end of conversion. This ensures that the

read operation will take place after conversion is finished.

AD7895 PERFORMANCE

Linearity

The linearity of the AD7895 is determined by the on-chip

12-bit D/A converter. This is a segmented DAC that is laser

trimmed for 12-bit integral linearity and differential linearity.

Typical relative accuracy numbers for the part are ±1/4 LSB

while the typical DNL errors are ±1/2 LSB.

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT, for example)

in ac applications. In a sampling A/D converter like the AD7895,

all information about the analog input appears in the baseband

from dc to 1/2 the sampling frequency. The input bandwidth of

the track/hold exceeds the Nyquist bandwidth and, therefore, an

antialiasing filter should be used to remove unwanted signals above

/2 in the input signal in applications where such signals exist.

Figure 10 shows a histogram plot for 8192 conversions of a dc

input using the AD7895. The analog input was set at the center

of a code transition. It can be seen that almost all the codes

appear in the one output bin, indicating very good noise

performance from the ADC.

957 962958 959 960 961

4000

3000

2000

1000

6000

5000

7000

8000

9000

Figure 10. Histogram of 8192 Conversions of a DC Input

In this case where the output data read for the device occurs

during conversion, this has the effect of injecting noise onto the

die while bit decisions are being made, and this increases the

noise generated by the AD7895. A histogram plot for 8192

conversions of the same dc input would show a larger spread of

codes with the rms noise for the AD7895 increasing. This effect

will vary depending on where the serial clock edges appear with

respect to the bit trials of the conversion process. It is possible

to achieve the same level of performance when reading during

conversion as when reading after conversion, depending on the

relationship of the serial clock edges to the bit trial points.

AD7895

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Dynamic Performance (Mode 1 Only)

With a combined conversion and acquisition time of 4.1 µs, the

AD7895 is ideal for wide bandwidth signal processing applica-

tions. These applications require information on the ADC’s

effect on the spectral content of the input signal. Signal to

(Noise + Distortion), Total Harmonic Distortion, Peak Har-

monic or Spurious Noise, and Intermodulation Distortion are

all specified. Figure 11 shows a typical FFT plot of a 10 kHz,

0 V to +5 V input after being digitized by the AD7895 operating

at a 198.656 kHz sampling rate. The Signal to (Noise + Distor-

tion) Ratio is 73.04 dB, and the Total Harmonic Distortion is

–84.91 dB.

The formula for Signal to (Noise + Distortion) Ratio (see

Terminology section) is related to the resolution or number of

bits in the converter. Rewriting the formula, below, gives a

measure of performance expressed in effective number of bits (N):

N = (SNR 1.76)/6.02

where SNR is Signal to (Noise + Distortion) Ratio.

–0

–120

0 9.9k10k 30k 50k 70k 90k

–20

–40

–60

–80

–100

–10

–30

–50

–70

–90

–110

SAMPLE

= 198656

= 10kHz

SNR = –73.04dB

THD = –84.91dB

Figure 11. AD7896 FFT Plot Effective Number of Bits

The effective number of bits for a device can be calculated from

its measured Signal to (Noise + Distortion) Ratio. Figure 12

shows a typical plot of effective number of bits versus frequency

for the AD7895 from dc to f

SAMPLING

/2. The sampling frequency

is 198.656 kHz. The plot shows that the AD7895 converts an

input sine wave of 10 kHz to an effective numbers of bits of

11.84, which equates to a Signal to (Noise + Distortion) level of

73.04 dB.

0 1000200 400 600 800

10.0

11.4

11.2

11.0

10.8

11.8

11.6

12.0

10.6

10.4

FREQUENCY – kHz

ENOB

10.2

Figure 12. Effective Number of Bits vs. Frequency

Power Considerations

In the automatic power-down mode, then, the part may be

operated at a sample rate that is considerably less than

100 kHz. In this case, the power consumption will be reduced

and will depend on the sample rate. Figure 13 shows a graph

of the power consumption versus sampling rates from 100 Hz to

90 kHz in the automatic power-down mode. The conditions

are 5 V supply 25°C, serial clock frequency of 8.33 MHz, and

the data was read after conversion.

0.1 9010 20 30 40

FREQUENCY – kHz

POWER – mW

50 60 70 80

Figure 13. Power vs. Sample Rate in Auto Power-Down

Mode

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD7895BRZ-10

Mfr. #:

Buy AD7895BRZ-10

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Bipolar Input 5V 12B Serial 3.8uS

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AD7895BRZ-10

AD7895BRZ-10

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