AD7895BRZ-10 Datasheet AD7895ARZ-10REEL, AD7895ANZ-2, AD7895ARZ-10 | P7-P9

AD7895

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CONVERTER DETAILS

The AD7895 is a fast, 12-bit single supply A/D converter. It

provides the user with signal scaling, track/hold, A/D converter

and serial interface logic functions on a single chip. The A/D

converter section of the AD7895 consists of a conventional

successive-approximation converter based around an R-2R

ladder structure. The signal scaling on the AD7895-10 and

AD7895-3 allows the part to handle ±10 V and ±2.5 V input

signals, respectively, while operating from a single +5 V supply.

The AD7895-2 accepts an analog input range of 0 V to +2.5 V.

The part requires an external +2.5 V reference. The reference

input to the part is buffered on-chip.

The AD7895 has two

operating modes, the high sampling mode and the auto sleep

mode, where the part automatically goes into sleep after the end of

conversion. These modes are discussed in more detail in the

“Timing and Control” section.

A major advantage of the AD7895 is that it provides all of the

above functions in an 8-pin package, either 8-pin mini-DIP or

SOIC. This offers the user considerable spacing saving advantages

over alternative solutions. The AD7895 consumes only 20 mW

maximum, making it ideal for battery-powered applications.

Conversion is initiated on the AD7895 by pulsing the

CONVST

input. On the falling edge of

CONVST, the on-chip track/hold

goes from track to hold mode, and the conversion sequence is

started. The conversion clock for the part is generated internally

using a laser-trimmed clock oscillator circuit. Conversion time

for the AD7895 is 3.8 µs in the high sampling mode (9.8 µs for

the auto sleep mode), and the track/hold acquisition time is

0.3 µs. To obtain optimum performance from the part, the read

operation should not occur during the conversion or during

300 ns prior to the next conversion. This allows the part to

operate at throughput rates up to 192 kHz and achieve data sheet

specifications.

CIRCUIT DESCRIPTION

Analog Input Section

The AD7895 is offered as three part types: the AD7895-10,

which handles a ±10 V input voltage range; the AD7895-3,

which handles input voltage range ±2.5 V; and the AD7895-2,

which handles a 0 V to +2.5 V input voltage range.

AGND

AD7895-10/AD7895-3

REF IN

TRACK/

HOLD

TO ADC

REFERENCE

CIRCUITRY

TO INTERNAL

COMPARATOR

Figure 2. AD7895-10/AD7895-3 Analog Input Structure

Figure 2 shows the analog input section for the AD7895-10 and

AD7895-3. The analog input range of the AD7895-10 is ±10 V

into an input resistance of typically 33 kΩ. The analog input

range of the AD7895-3 is ±2.5 V into an input resistance of

typically 12 kΩ. This input is benign with no dynamic charging

currents, as the resistor stage is followed by a high input imped-

ance stage of the track/hold amplifier. For the AD7895-10,

R1 = 30 kΩ, R2 = 7.5 kΩ and R3 = 10 kΩ. For the AD7895-3,

R1 = R2 = 6.5 kΩ and R3 is open circuit.

For the AD7895-10 and AD7895-3, the designed code transi-

tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,

3 LSBs . . .). Output coding is 2s complement binary with 1 LSB

= FS/4096. The ideal input/output transfer function for the

AD7895-10 and AD7895-3 is shown in Table I.

Table I. Ideal Input/Output Code Table for the AD7895-10/-3

Digital Output

Analog Input

Code Transition

+FSR/2 – 1 LSB

011 . . . 110 to 011 . . . 111

+FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110

+FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101

GND + 1 LSB 000 . . . 000 to 000 . . . 001

GND 111 . . . 111 to 000 . . . 000

GND – 1 LSB 111 . . . 110 to 111 . . . 111

–FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011

–FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010

–FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001

NOTES

FSR is full-scale range = 20 V (AD7895-10) and = 5 V (AD7895-3)

with REF IN = +2.5 V.

1 LSB = FSR/4096 = 4.883 mV (AD7895-10) and 1.22 mV (AD7895-3)

with REF IN = +2.5 V.

The analog input section for the AD7895-2 contains no biasing

resistors, and the V

pin drives the input to the track/hold

amplifier directly. The analog input range is 0 V to +2.5 V into

a high impedance stage with an input current of less than

500 nA. This input is benign with no dynamic charging cur-

rents. Once again, the designed code transitions occur on succes-

sive integer LSB values. Output coding is straight (natural) binary

with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table II shows

the ideal input/output transfer function for the AD7895-2.

Table II. Ideal Input/Output Code Table for AD7895-2

Digital Output

Analog Input

Code Transition

+FSR – 1 LSB

111 . . . 110 to 111 . . . 111

+FSR – 2 LSB 111 . . . 101 to 111 . . . 110

+FSR – 3 LSB 111 . . . 100 to 111 . . . 101

GND + 3 LSB 000 . . . 010 to 000 . . . 011

GND + 2 LSB 000 . . . 001 to 000 . . . 010

GND + 1 LSB 000 . . . 000 to 000 . . . 001

NOTES

FSR is full-scale range and is 2.5 V for AD7895-2 with VREF = +2.5 V.

1 LSB = FSR/4096 and is 0.61 mV for AD7895-2 with VREF = +2.5 V.

Track/Hold Section

The track/hold amplifier on the analog input of the AD7895

allows the ADC to accurately convert an input sine wave of full-

scale amplitude to 12-bit accuracy. The input bandwidth of the

track/hold is greater than the Nyquist rate of the ADC even

when the ADC is operated at its maximum throughput rate of

192 kHz (i.e., the track/hold can handle input frequencies in

excess of 100 kHz).

AD7895

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The track/hold amplifier acquires an input signal to 12-bit

accuracy in less than 0.3 µs. The operation of the track/hold is

essentially transparent to the user. With the high sampling

operating mode, the track/hold amplifier goes from its tracking

mode to its hold mode at the start of conversion (i.e. the falling

edge of

CONVST). The aperture time for the track/hold (i.e.

the delay time between the external

CONVST signal and the

track/hold actually going into hold) is typically 15 ns. At the

end of conversion (on the falling edge of BUSY), the part returns

to its tracking mode. The acquisition time of the track/hold

amplifier begins at this point. For the auto shut down mode, the

rising edge of

CONVST wakes up the part and the track, and

hold amplifier goes from its tracking mode to its hold mode 6 µs

after the rising edge of

CONVST (provided that the CONVST

high time is less than 6 µs). Once again, the part returns to its

tracking mode at the end of conversion when the BUSY signal

goes low.

Reference Input

The reference input to the AD7895 is buffered on-chip with a

maximum reference input current of 1 µA. The part is specified

with a +2.5 V reference input voltage. Errors in the reference

source will result in gain errors in the AD7895’s transfer

function and will add to the specified full-scale errors on the

part. Suitable reference sources for the AD7895 include the

AD780 and AD680 precision +2.5 V references.

Timing and Control Section

Figure 3 shows the timing and control sequence required to

obtain optimum performance from the AD7895. In the se-

quence shown, conversion is initiated on the falling edge of

CONVST, and new data from this conversion is available in

the output register of the AD7895 3.8 µs later. Once the read

operation has taken place, a further 300 ns should be allowed

before the next falling edge of

CONVST to optimize the settling

of the track/hold amplifier before the next conversion is initi-

ated. With the serial clock frequency at its maximum of

15 MHz, the achievable throughput rate for the part is 3.8 µs

(conversion time) plus 1.1 µs (read time) plus 0.3 µs (acquisi-

tion time). This results in a minimum throughput time of 8.2 µs

(equivalent to a throughput rate of 192 kHz). A serial clock of

less than 15 MHz can be used, but this will in turn mean that

the throughput time will increase.

The read operation consists of sixteen serial clock pulses to the

output shift register of the AD7895. After sixteen serial clock

pulses, the shift register is reset, and the SDATA line is three-

stated. If there are more serial clock pulses after the sixteenth

clock, the shift register will be moved on past its reset state.

However, the shift register will be reset again on the falling edge

of the

CONVST signal to ensure that the part returns to a

known state every conversion cycle. As a result, a read opera-

tion from the output register should not straddle across the

falling edge of

CONVST as the output shift register will be reset

in the middle of the read operation, and the data read back into

the microprocessor will appear invalid.

OPERATING MODES

Mode 1 Operation (High Sampling Performance)

The timing diagram in Figure 3 is for optimum performance in

operating Mode 1 where the falling edge of

CONVST starts

conversion and puts the Track/Hold amplifier into its hold

mode. This falling edge of CONVST also causes the BUSY

signal to go high to indicate that a conversion is taking place.

The BUSY signal goes low when the conversion is complete,

which is 3.8 µs max after the falling edge of

CONVST, and new

data from this conversion is available in the output register of

the AD7895. A read operation accesses this data. This read

operation consists of 16 clock cycles, and the length of this read

operation will depend on the serial clock frequency. For the

fastest throughput rate (with a serial clock of 15 MHz, 5 V

operation) the read operation will take 1.1 µs. The read opera-

tion must be complete at least 300 ns before the falling edge of

the next

CONVST, and this gives a total time of 5.2 µs for the

full throughput time (equivalent to 192 kHz). This mode of

operation should be used for high sampling applications.

Mode 2 Operation (Auto Sleep After Conversion)

The timing diagram in Figure 4 is for optimum performance in

operating mode 2 where the part automatically goes into sleep

mode once BUSY goes low after conversion and “wakes-up”

before the next conversion takes place. This is achieved by keep-

ing

CONVST low at the end of conversion, whereas it was high

at the end of conversion for Mode 1 Operation. The rising edge

CONVST “wakes up” the part. This wake-up time is 6 µs at

which point the Track/Hold amplifier goes into its hold mode,

provided the

CONVST has gone low. The conversion takes

3.8 µs after this giving a total of 9.8 µs from the rising edge of

CONVST to the conversion being complete, which is indi-

cated by the BUSY going low. Note that since the wake-up time

from the rising edge of

CONVST is 6 µs, when the CONVST

pulse width is greater than 6 µs, the conversion will take more

CONVST

BUSY

SCLK

SERIAL READ

OPERATION

CONVERSION

ENDS

3.8µs LATER

OUTPUT

SERIAL

SHIFT

IS RESET

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES INTO

HOLD

= 40ns MIN

300ns MIN

CONVERT

= 3.8µs

READ OPERATION

SHOULD END 300ns

PRIOR TO NEXT

FALLING EDGE OF

CONVST

Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance

AD7895

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than the 9.8 µs shown in diagram from the rising edge of

CONVST. This is because the Track/Hold amplifier goes into

its hold mode on the falling edge of

CONVST, and the conver-

sion will not be complete for a further 3.8 µs. In this case, the

BUSY will be the best indicator for when the conversion is

complete. Even though the part is in sleep mode, data can still

be read from the part. The read operation consists of 16 clock

cycles as in Mode 1 Operation. For the fastest serial clock of

15 MHz, the read operation will take 1.1 µs and this must be

complete at least 300 ns before the falling edge of the next

CONVST to allow the Track/Hold amplifier to have enough

time to settle. This mode is very useful when the part is convert-

ing at a slow rate as the power consumption will be significantly

reduced from that of Mode 1 Operation.

Serial Interface

The serial interface to the AD7895 consists of just three wires: a

serial clock input (SCLK), the serial data output (SDATA) and

a conversion status output (BUSY). This allows for an easy-to-

use interface to most microcontrollers, DSP processors and shift

registers.

Figure 5 shows the timing diagram for the read operation to the

AD7895. The serial clock input (SCLK) provides the clock

source for the serial interface. Serial data is clocked out from the

SDATA line on the falling edge of this clock and is valid on

both the rising and falling edges of SCLK. The advantage of

having the data valid on both the rising and falling edges of the

SCLK is that it gives the user greater flexibility in interfacing to

the part and allows a wider range of microprocessor and micro-

controller interfaces to be accommodated. This also explains the

two timing figures, t

and t

that are quoted on the diagram.

The time t

specifies how long after the falling edge of the

SCLK that the next data bit becomes valid, whereas the time t

specifies how long after the falling edge of the SCLK that the

current data bit is valid for. The first leading zero is clocked out

on the first rising edge of SCLK. Note that the first zero will be

valid on the first falling edge of SCLK even though the data

access time is specified at 60 ns for the other bits. The reason

that the first bit will be clocked out faster than the other bits is

due to the internal architecture of the part. Sixteen clock pulses

must be provided to the part to access to full conversion result.

The AD7895 provides four leading zeros, followed by the 12-bit

conversion result starting with the MSB (DB11). The last data

bit to be clocked out on the penultimate falling clock edge is the

LSB (DB0). On the sixteenth falling edge of SCLK, the LSB

(DB0) will be valid for a specified time to allow the bit to be

read on the falling edge of the SCLK, then the SDATA line is

disabled (three-stated). After this last bit has been clocked

out, the SCLK input should return low and remain low until the

next serial data read operation. If there are extra clock pulses

after the sixteenth clock, the AD7895 will start over again with

outputting data from its output register, and the data bus will no

longer be three-stated even when the clock stops. Provided the

serial clock has stopped before the next falling edge of

CONVST,

the AD7895 will continue to operate correctly with the output

shift register being reset on the falling edge of

CONVST.

However, the SCLK line must be low when

CONVST goes low in

order to reset the output shift register correctly.

The serial clock input does not have to be continuous during the

serial read operation. The sixteen bits of data (four leading

zeros and 12 bit conversion result) can be read from the AD7895

in a number of bytes.

The AD7895 counts the serial clock edges to know which bit

from the output register should be placed on the SDATA

output. To ensure that the part does not lose synchronization,

the serial clock counter is reset on the falling edge of the

CONVST input, provided the SCLK line is low. The user

should ensure that the SCLK line remains low until the end of

the conversion. When the conversion is complete, BUSY goes

low, the output register will be loaded with the new conversion

result and can be read from with sixteen clock cycles of SCLK.

CONVST

BUSY

SCLK

SERIAL READ

OPERATION

CONVERSION

ENDS

9.8µs LATER

READ OPERATION

SHOULD END 300ns

PRIOR TO NEXT

FALLING EDGE OF

CONVST

OUTPUT

SERIAL

SHIFT

IS RESET

PART

WAKES

CONVERSION

IS INITIATED

TRACK/HOLD

GOES INTO

HOLD

= 6µs

WAKE-UP

TIME

CONVERT

= 9.8µs

300ns MIN

Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated

4 LEADING ZEROS

DOUT (O/P)

SCLK (I/P)

1 2 3 4 5 6 15 16

DB0DB10DB11

3-STATE

= t

= 35ns MIN, t

= 60ns MAX, t

= 10ns MIN, t

= 50ns MAX @ 5V, A, B, VERSIONS

Figure 5. Data Read Operation

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD7895BRZ-10

Mfr. #:

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Manufacturer:

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Description:

Analog to Digital Converters - ADC Bipolar Input 5V 12B Serial 3.8uS

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