Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
8535AGI-01 www.idt.com REV. F MAY 28, 2013
4
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. LVPECL DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
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V
CC
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I
EE
tnerruCylppuSrewoP 55Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI
1KLC,0KLC2V
CC
3.0+V
LES_KLC,NE_KLC2V
CC
3.0+V
V
LI
egatloVwoLtupnI
1KLC,0KLC3.0-3.1V
LES_KLC,NE_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI
LES_KLC,1KLC,0KLCV
NI
V=
CC
V564.3=051Aµ
NE_KLCV
NI
V=
CC
V564.3=5Aµ
I
LI
tnerruCwoLtupnI
LES_KLC,1KLC,0KLCV
NI
V,V0=
CC
V564.3=5-Aµ
NE_KLCV
NI
V,V0=
CC
V564.3=051-Aµ
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V
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1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
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CC
.V2-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
73.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8535AGI-01 www.idt.com REV. F MAY 28, 2013
5
Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
TABLE 5. AC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
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Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V
LVPECL Fanout Buffer
ICS8535I-01
8535AGI-01 www.idt.com REV. F MAY 28, 2013
6
Additive Phase Jitter at
156.25MHz = 0.09ps (typical)
ADDITIVE PHASE JITTER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-
140
-150
-
160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applica tions. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is e
xpressed in decibels (dBm) or a ratio of the power
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated abo
ve. The
in the 1Hz band to the power in the fundamental. When the
required offset is specified, the phase noise is called a
dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired ap-
plication over the entire time record of the signal. It is math-
ematically possible to calculate an e
xpected bit error rate given
a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source
and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ

8535AGI-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1:4 LVCMOS-to-3.3V LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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