AD9214BRSZ-RL65 Datasheet AD9214BRSZ-80, AD9214BRSZ-RL80, AD9214BRSZ-RL105 | P13-P15

REV. D

AD9214

–12–

THEORY OF OPERATION

The AD9214 architecture is a bit-per-stage pipeline converter

utilizing switch capacitor techniques. These stages determine

the 7 MSBs and drive a 3-bit flash. Each stage provides suffi-

cient overlap and error correction allowing optimization of

comparator accuracy. The input buffer is differential and both

inputs are internally biased. This allows the most flexible use of

ac or dc and differential or single-ended input modes. The out-

put staging block aligns the data, carries out the error correction

and feeds the data to output buffers. The output buffers are

powered from a separate supply, allowing support of different

logic families. During power-down, the outputs go to a high

impedance state.

APPLYING THE AD9214

Encoding the AD9214

Any high-speed A/D converter is extremely sensitive to the

quality of the sampling clock provided by the user. A Track/

Hold circuit is essentially a mixer. Any noise, distortion, or

timing jitter on the clock will be combined with the desired

signal at the A/D output. For that reason, considerable care has

been taken in the design of the ENCODE input of the AD9214,

and the user is advised to give commensurate thought to the clock

source. The ENCODE input is fully TTL/CMOS compatible, and

should normally be driven directly from a low jitter, crystal-

controlled TTL/CMOS oscillator.

The ENCODE input is internally biased, allowing the user to

ac-couple in the clock signal. The cleanest clock source is often

a crystal oscillator producing a pure sine wave. Figure 7 illustrates

ac coupling such a source to the ENCODE input.

ENCODE

LOW JITTER CRYSTAL SINE OR

PULSE SOURCE 1V p-p

AD9214

Figure 7. AC-Coupled Encode Circuit

Reference Circuit

The reference circuit of the AD9214 is configured by REFSENSE

(Pin 3). By externally connecting REFSENSE to AGND, the

ADC is configured to use the internal reference (~1.25 V), and

the REF pin connection (Pin 4) is configured as an output for

the internal reference voltage.

If REFSENSE is externally connected to AV

, the ADC is

configured to use an external reference. In this mode, the REF

pin is configured as a reference input, and must be driven by an

external 1.25 V reference.

In either configuration, the analog input voltage range (either

1 V p-p or 2 V p-p as determined by DFS/Gain) will track the

reference voltage linearly, and an external bypass capacitor should

be connected between REF and AGND to reduce noise on the

reference. In practice, no appreciable degradation in performance

occurs when an external reference is adjusted ±5%.

DFS/GAIN

The DFS/GAIN (Data Format Select/Gain) input (Pin 2)

controls both the output data format and gain (analog input volt-

age range) of the ADC. The table below describes its operation.

Table I. Data Format and Gain Configuration

External Differential

DFS/GAIN Analog Input

Connection Voltage Range Output Data Format

AGND 1 V p-p Offset Binary

1 V p-p Two’s Complement

REF 2 V p-p Two’s Complement

Floating 2 V p-p Offset Binary

Driving the Analog Inputs

The analog input to the AD9214 is a differential buffer. As

shown in the equivalent circuits, each of the differential inputs is

internally dc biased at ~AV

/3 to allow ac-coupling of the

analog input signal. The analog signal may be dc-coupled as

well. In this case, the dc load will be equivalent to ~10 kΩ to

/3, and the dc common-mode level of the analog signals

should be within the range of AV

/3 ±200 mV. For best dynamic

performance, impedances at A

and AIN should match.

Driving the analog input differentially optimizes ac performance,

minimizing even order harmonics and taking advantage of

common-mode rejection of noise. A differential signal may be

transformer-coupled, as illustrated in Figure 8, or driven from a

high-performance differential amplifier such as the AD8138

illustrated in Figure 9.

0.1␮F

25⍀

1:1

50⍀

ANALOG

SIGNAL

SOURCE

AD9214

Figure 8. Single-Ended-to-Differential Conversion Using

a Transformer

Special care was taken in the design of the analog input section

of the AD9214 to prevent damage and corruption of data when

the input is overdriven. The optimal input range is 1.0 V p-p, but

the AD9214 can support a 2.0 V p-p input range with some degra-

dation in performance (see DFS/GAIN pin description above).

REV. D

AD9214

–13–

AD9214

50⍀

ANALOG

SIGNAL

SOURCE

15pF

50⍀

VOCM

+ –

– +

AD8138

500⍀

0.1␮F

10k⍀

5k⍀

Figure 9. DC-Coupled Analog Input Circuit

POWER SUPPLIES

The AD9214 has two power supplies, AV

and DrV

. AV

and AGND supply power to all the analog circuitry, the inputs

and the internal timing and digital error correction circuits.

supply current will vary slightly with encode rate, as noted in

the Typical Performance Characteristics section.

DrV

and DGND supply only the CMOS digital outputs,

allowing the user to adjust the voltage level to match down-

stream logic.

DrV

current will vary depending on the voltage level, external

loading capacitance, and the encode frequency. Designs that mini-

mize external load capacitance will reduce power consumption

and reduce supply noise that may affect ADC performance. The

maximum DrV

current can be calculated as

I V C fencode N

DrV DrV LOAD

DD DD

=× × ×

where N is the number of output bits, 10 in the case of the

AD9214. This maximum current is for the condition of every

output bit switching on every clock cycle, which can only occur

for a full scale square wave at the Nyquist frequency, f

ENCODE

/2.

In practice, I

DrV

will be the average number of output bits

switching, which will be determined by the encode rate and the

characteristics of the analog input signal. The performance

curves section provides a reference of I

DrV

versus encode rate

for a 10.3 MHz sine wave driving the analog input.

Both power supply connections should be decoupled to ground

at or near the package connections, using high quality, ceramic

chip capacitors. A single ground plane is recommended for all

ground (AGND and DGND) connections.

The PWRDN control pin configures the AD9214 for a sleep

mode when it is logic HIGH. PWRDN floats logic LOW for

normal operation. In sleep mode, the ADC is not active, and

will consume less power. When switching from sleep mode to

normal operation, the ADC will need ~15 clock cycles to recover to

valid output data.

Digital Outputs

Care must be taken when designing the data receivers for the

AD9214. It is recommended that the digital outputs drive a

series resistor (e.g., 100 Ω) followed by a gate like the 74LCX821.

To minimize capacitive loading, there should be only one gate

on each output pin. An example of this is shown in the evaluation

board schematic in Figure 10. The series resistors should be

placed as close to the AD9214 as possible to limit the amount of

current that can flow into the output stage. These switching

currents are confined between ground (DGND) and the DrV

pins. Standard TTL gates should be avoided since they can

appreciably add to the dynamic switching currents of the AD9214.

It should also be noted that extra capacitive loading will increase

output timing and invalidate timing specifications. Digital output

timing is guaranteed with 10 pF loads.

LAYOUT INFORMATION

The schematic of the evaluation board (Figure 10) represents a

typical implementation of the AD9214. A multilayer board is

recommended to achieve best results. It is highly recommended

that high quality, ceramic chip capacitors be used to decouple

each supply pin to ground directly at the device. The pinout of

the AD9214 facilitates ease of use in the implementation of high

frequency, high resolution design practices. All of the digital

outputs and their supply and ground pin connections are segre-

gated to one side of the package, with the inputs on the opposite

side for isolation purposes.

Care should be taken when routing the digital output traces. To

prevent coupling through the digital outputs into the analog

portion of the AD9214, minimal capacitive loading should be

placed on these outputs. It is recommended that a fan-out of

only one gate should be used for all AD9214 digital outputs.

The layout of the encode circuit is equally critical. Any noise

received on this circuitry will result in corruption in the digitiza-

tion process and lower overall performance. The Encode clock

must be isolated from the digital outputs and the analog inputs.

EVALUATION BOARD

The AD9214 evaluation board offers designers an easy way to

evaluate device performance. The user must supply an analog

input signal, encode clock reference, and power supplies. The

digital outputs of the AD9214 are latched on the evaluation

board, and are available with a data ready signal at a 40-pin

edge connector. Please refer to the evaluation board schematic,

layout, and Bill of Materials.

Power Connections

Power to the board is supplied via three detachable, 4-pin power

strips (U4, U9, and U10). These 12 pins should be driven as

outlined in the Table II.

Table II. Power Supply Connections for AD9214

Evaluation Board

External Supply

Pin Designator Required

1 LVC 3 V

3 +5 V +5 V

(Optional Z1 Supply)

5 –5 V –5 V

(Optional Z1 Supply)

7 VCC 3 V

9 VDD 3 V

11 DAC 5 V

2, 4, 6, GND Ground

8, 10, 12

Please note that the +5 V and –5 V supplies are optional, and

only required if the user adds differential op amp Z1 to the board.

REV. D

AD9214

–14–

Reference Circuit

The evaluation board is configured at assembly to use the

AD9214’s on-board reference. To supply an external reference,

the user must connect the REFSENSE pin to VCC by removing

the jumper block connecting E25 to E26, and placing it between

E19 and E24. In this configuration, an external 1.25 V reference

must be connected to jumper connection E23. Jumper connections

E19–E21, E24, and resistors R13–R14 are omitted at assembly,

and not used in the evaluation of the AD9214.

Gain/Data Format

The evaluation board is assembled with the DFS/GAIN pin

connected to ground; this configures the AD9214 for a 1 V p-p

analog input range, and offset binary data format. The user may

remove this jumper and replace it to make one of the connections

described in the table below to configure the AD9214 for different

gain and output data format options.

Table III. Data Format and Gain Configuration for

Evaluation Board

DFS/GAIN

Jumper DFS/GAIN Differential Output Data

Placement Connection A

Range Format

E18 to E12 AGND 1 V p-p Offset Binary

E16 to E11 AV

1 V p-p Two’s Complement

E15 to E14 REF 2 V p-p Two’s Complement

E17 to E13 Floating 2 V p-p Offset Binary

Power-Down

The evaluation board is configured at assembly so that the

PWRDN input floats low for normal operating condition. The

user may add a jumper between option holes E5 and E6 to

connect PWRDN to AVCC, configuring the AD9214 for power-

down mode.

Encode Signal and Distribution

The encode input signal should drive SMB connector J5, which

has an on-board 50 Ω termination. A standard CMOS compatible

pulse source is recommended. Alternatively, the user can adjust

the dc level of an ac-coupled clock source by adding resistor

R11, normally omitted. J5 drives the AD9214 ENCODE input

and one gate of U12, which buffers and distributes the clock

signal to the on-board latch (U3), the reconstruction DAC

(U11), and the output data connector (U2). The board comes

assembled with timing options optimized for the DAC and latch;

the user may invert the DR signal at Pin 37 of edge connector

U2 by removing the jumper block between E34 and E35, and

reinstalling it between E35 and E36.

Analog Input

The analog input signal is connected to the evaluation board by

SMB connector J1. As configured at assembly, the signal is ac

coupled by capacitor C10 to transformer T1. This 1:1 transformer

provides a 50 Ω termination for connector J1 via 25 Ω resistors

R1 and R4. T1 also converts the signal at J1 into a differential

signal for the analog inputs of the AD9214. Resistor R3, normally

omitted, can be used to terminate J1 if the transformer is removed.

The user can reconfigure the board to drive the AD9214 single-

endedly by removing the jumper block between E1 and E3, and

replacing it between E3 and E2. In this configuration, capacitor

C2 stabilizes the self-bias of AIN, and resistor R2 provides a

matched impedance for a 50 Ω source at J1.

Transformer T1 can be bypassed by moving the jumper normally

between E40 and E38 to connect E40 to E37, and moving the

jumper normally between E39 and E10 to connect E7 to E10.

In this configuration, the analog input of the AD9214 is driven

single ended, directly from J1; and R3 (normally omitted) should

be installed to terminate any cable connected to J1.

Using the AD8138

An optional driver circuit for the analog input, based on the

AD8138 differential amplifier, is included in the layout of the

AD9214 evaluation board. This portion of the evaluation circuit

is not populated when the board is manufactured, but can be

easily be added by the user. Resistors R5, R16, R18, and R25

are the feedback network that sets the gain of the AD8138.

Resistors R23 and R24 set the common-mode voltage at the

output of the op amp. Resistors R27 and R28, and capacitor

C15, form a low-pass filter at the output of the AD8138, limiting

its noise contribution into the AD9214.

Once the drive circuit is populated, the user should remove the

jumper block normally between E40 and E38, and place it between

E40 and E41. This will ac-couple the analog input signal from

SMB connector J1 to the AD8138 drive circuit. The user will also

need to remove the jumper blocks that normally connect E39 to

E10 and E1 to E3 to remove transformer T1 from the circuit.

DAC Reconstruction Circuit

The data available at output connector U2 is also reconstructed by

DAC U11, the AD9752. This 12-bit, high-speed digital-to-analog

converter is included as a tool in setting up and debugging the

evaluation board. It should not be used to measure the per-

formance of the AD9214, as its performance will not accurately

reflect the performance of the ADC. The DAC’s output, available

at J2, will drive 50 Ω. The user can add a jumper block between

E8 and E9 to activate the SLEEP function of the DAC.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD9214BRSZ-RL65

Mfr. #:

Buy AD9214BRSZ-RL65

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 10-Bit 65 MSPS 3.3V

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AD9214BRSZ-RL65

AD9214BRSZ-RL65

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