REV. D
AD9214
–6–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1 OR CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was
outside the converter’s range for the current output data.
2 DFS/GAIN Data Format Select and Gain Mode Select. Connect externally to AV
DD
for two’s complement
data format and 1 V p-p analog input range. Connect externally to AGND for Offset Binary data
format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for two’s complement
data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset
Binary data format and a 2 V p-p analog input range.
3 REFSENSE Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND,
which enables the internal 1.25 V reference, and configures REF (Pin 4) as an analog reference
output pin. Connecting REFSENSE externally to AV
DD
disables the internal reference, and config-
ures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean
and accurate 1.25 V (±5%) reference input.
4 REF Reference input or output as configured by REFSENSE (Pin 3). When configured as an output
(REFSENSE = AGND), the internal reference (nominally 1.25 V) is enabled and is available to
the user on this pin. When configured as an input (REFSENSE = AV
DD
), the user must drive
REF with a clean and accurate 1.25 V (±5%) reference. This pin should be bypassed to AGND
with an external 0.1 µF capacitor, whether it is configured as an input or output.
5, 8, 11 AGND Analog Ground
6, 7, 12 AV
DD
Analog Power Supply, Nominally 3 V
9A
IN
Positive terminal of the differential analog input for the ADC.
10 AIN Negative terminal of the differential analog input for the ADC. This pin can be left open if
operating in single-ended mode, but it is preferable to match the impedance seen at the positive
terminal (see Driving the Analog Inputs).
13 ENCODE Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.
14 PWRDN CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH
for power-down mode (digital outputs in high impedance state). PWRDN has an internal
10 k pull-down resistor to ground.
15, 23 DGND Digital Output Ground
16, 24 DrV
DD
Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V.
17–22, 25–28 D0 (LSB)–D5, CMOS Digital Outputs of ADC
D6–D9 (MSB)
PIN CONFIGURATION
28-Lead Shrink Small Outline Package
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9214
PWRDN
ENCODE
AV
DD
AGND
A
IN
A
IN
AGND
OR
DFS/GAIN
REFSENSE
REF
AV
DD
AV
DD
AGND
DGND
DrV
DD
D0 (LSB)
D1
D2
D3
D4
D9 (MSB)
D8
D7
D6
D5
DGND
DrV
DD
REV. D
AD9214
–7–
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differen-
tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak-to-peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
ENOB
SINAD dB
Full Scale
Actual
MEASURED
=
+
. log
.
176 20
602
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic 1 state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing t
ENCH
in text. At a
given clock rate, these specs define an acceptable Encode duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
Z
FULL SCALE
FULL SCALE rms
INPUT
=
10
0 001
2
log
.
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for any range within the ADC)
VZ
FS SNR Signal
NOISE
dBm dBc dBFS
×
−−
0 001 10
10
.
Where Z is the input impedance, FS is the full-scale of the
device for the frequency in question, SNR is the value for the
particular input level and Signal is the signal level within the
ADC reported in dB below full-scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May
be reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
REV. D
AD9214
–8–
Transient Response Time
Transient response is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
15k
30k
40
15k
30k
40
A
IN
AV
DD
A
IN
Figure 2. Analog Input Stage
2.6k
2.6k
600
ENCODE
Figure 3. Encode Inputs
40
DV
DD
DX
Figure 4. Digital Output Stage
EQUIVALENT CIRCUITS
10k
V
REF
10k
REF
AV
DD
Figure 5. REF Configured as an Output
10k
REF
AV
DD
Figure 6. REF Configured as an Input
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.

AD9214BRSZ-RL65

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-Bit 65 MSPS 3.3V
Lifecycle:
New from this manufacturer.
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