LT3837
19
3837fd
APPLICATIONS INFORMATION
V
IN
R
A
LT3837
(4a) UV Turning ON
UVLO
I
UVLO
R
B
V
IN
R
A
LT3837
(4b) UV Turning OFF (4c) UV Filtering
UVLO
UVLO
R
B
V
IN
R
A2
R
A1
C
UVLO
R
B
3837 F04
I
UVLO
Figure 4
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 4, the voltage hysteresis at V
IN
is
equal to the change in bias current times R
A
. The design
procedure is to select the desired V
IN
referred voltage
hysteresis, V
UVHYS
. Then:
R
A
=
V
UVHYS
I
UVLO
where:
I
UVLO
= I
UVLOL
– I
UVLOH
is approximately 3.4µA
R
B
is then selected with the desired turn-on voltage:
R
B
=
R
A
V
IN(ON)
V
UVLO
1
If we wanted a V
IN
-referred trip point of 8.4V, with 0.3V
of hysteresis (on at 8.4V, off at 8.1V):
R
A
=
0.3V
3.A
= 88.2k, use 86.6k
R
B
=
86.6k
8.4V
1.24V
1
= 14.99k, use 15k
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 4c shows an alternate method of filtering by split-
ting the R
A
resistor with the capacitor. The split should
put more of the resistance on the UVLO side.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifier (V
C
pin) to ground as shown in Figure 5. Be-
cause of the sampling behavior of the feedback amplifier,
compensation is different from traditional current mode
switcher controllers. Normally only C
VC
is required. R
VC
can be used to add a “zero” but the phase margin improve-
ment traditionally offered by this extra resistor is usually
already accomplished by the nonzero secondary circuit
impedance. C
VC2
can be used to add an additional high
frequency pole and is usually sized at 0.1 times C
VC
.
Figure 5. V
C
Compensation Network
9
R
VC
V
C
C
VC
3825 F05
C
VC2
In further contrast to traditional current mode switchers,
V
C
pin ripple is generally not an issue with the LT3837.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
V
C
voltage changes during the flyback pulse, but is then
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the V
C
voltage stable
during the current comparator sense action (current mode
switching).
AN19 provides a method for empirically tweaking frequency
compensation. Basically, it involves introducing a load
current step and monitoring the response.
Slope Compensation
This part incorporates current slope compensation. Slope
compensation is required to ensure current loop stability
when the DC is greater than 50%. In some switcher con-
trollers, slope compensation reduces the maximum peak
current at higher duty cycles. The LT3837 eliminates this
need by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
LT3837
20
3837fd
APPLICATIONS INFORMATION
Minimum Load Considerations
At light loads, the LT3837 derived regulator goes into
forced continuous conduction mode. The primary side
switch always turns on for a short time as set by the
t
ON(MIN)
resistor. If this produces more power than the
load requires, power will flow back into the primary during
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
though light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the V
C
node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds the
V
C
node voltage, the primary side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
C
reaches its 2.56V clamp. At clamp, the primary side
MOSFET will turn off at the rated 98mV V
SENSE
level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across R
SENSE
to exceed the max 98mV rating
because of the minimum switch-on time blanking. If the
voltage on V
SENSE
reaches 206mV after the minimum
turn-on time, the SFST capacitor is discharged, which also
discharges the V
C
capacitor. This then reduces the peak
current on the next cycle and will reduce overall stress in
the primary switch.
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhib-
ited by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
DC
MIN
= t
ON(MIN)
f
OSC
<
I
SC
R
SEC
+R
DS(ON)
( )
V
IN
N
SP
where:
t
ON(MIN)
= primary side switch minimum on-time
I
SC
= short-circuit output current
Other variables as previously defined.
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switch-on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
Output Voltage Error Sources
The LT3837’s feedback sensing introduces additional
sources of errors. The following is a summary list.
The internal bandgap voltage reference sets the reference
voltage for the feedback amplifier. The specifications detail
its variation.
The external feedback resistive divider ratio proportional
directly affects regulated voltage. Use 1% components.
Leakage inductance on the transformer secondary reduces
the effective secondary-to-feedback winding turns ratio
(N
S
/N
F
) from its ideal value. This increases the output volt-
age target by a similar percentage. Since secondary leakage
inductance is constant from part to part (with a tolerance)
adjust the feedback resistor ratio to compensate.
The transformer secondary current flows through the im-
pedances of the winding resistance, synchronous MOSFET
R
DS(ON)
and output capacitor ESR. The DC equivalent
current for these errors is higher than the load current
because conduction occurs only during the converters
“off” time. So divide the load current by (1 – DC).
LT3837
21
3837fd
APPLICATIONS INFORMATION
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LT3837 load compensation circuitry
(see Load Compensation).
If multiple output windings are used, the flyback winding
will have a signal that represents an amalgamation of all
these windings impedances. Take care that you examine
worst-case loading conditions when tweaking the volt-
ages.
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
on-resistance R
DS(ON)
, input capacitance, drain-to-source
breakdown voltage (BV
DSS
), maximum gate voltage (VGS)
and maximum drain current (I
D(MAX)
).
For the primary-side power MOSFET, the peak current
is:
I
PK
=
I
OUT
1–DC
MAX
1+
X
MIN
2
where X is peak-to-peak current ratio as defined earlier.
For each secondary-side power MOSFET, the peak cur-
rent is:
I
PK
=
I
OUT
1–DC
MAX
1+
X
MIN
2
Select a primary-side power MOSFET with a B
VDSS
greater
than:
BV
DSS
I
PK
L
LKG
C
P
+ V
IN(MAX)
+
V
OUT(MAX)
N
SP
where N
SP
reflects the turns ratio of that secondary-to-pri-
mary winding. L
LKG
is the primary-side leakage inductance
and C
P
is the primary-side capacitance (mostly from the
C
OSS
of the primary-side power MOSFET). A snubber
may be added to reduce the leakage inductance spike as
discussed earlier.
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
≥ V
OUT
+ V
IN(MAX)
• N
SP
Choose the primary side MOSFET R
DS(ON)
at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
I
RMSPRI
=
P
IN
V
IN(MIN)
DC
MAX
For each secondary-side power MOSFET RMS current is
given by:
I
RMSSEC
=
I
OUT
1–DC
MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET may operate at high V
DS
, a
transition power loss term is included for accuracy. C
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 6).
Q
A
V
GS
a b
3825 F06
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 6. Gate Charge Curve
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
C
MILLER
=
Q
B
Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specified V
DS
.

LT3837EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Iso No-Opto Sync Fly Cntr
Lifecycle:
New from this manufacturer.
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