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LT3837EFE#TRPBF

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LT3837
22
3837fd
APPLICATIONS INFORMATION
With C
MILLER
determined, calculate the primary-side power
MOSFET power dissipation:
P
DPRI
=I
RMS(PRI)
2
•R
DS(ON)
1+d
( )
+
V
IN(MAX)
•
P
IN(MAX)
DC
IN
•R
DR
•
C
MILLER
V
GATE(MAX)
– V
TH
• f
OSC
where:
R
DR
is the gate driver resistance approximately 10Ω
V
TH
is the MOSFET gate threshold voltage
f
OSC
is the operating frequency.
(1 + d) is generally given for a MOSFET in the form of a
normalized RDS(ON) vs temperature curve. If you don’t
have a curve, use d = 0.005/°C as an estimate.
The secondary-side power MOSFETs typically operate
at substantially lower V
DS
, so you can neglect transition
losses. The dissipation is calculated using:
P
D(SEC)
= I
RMS(SEC)
2
• R
DS(ON)
(1 + d)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T
J
= T
A
+ P
D
• q
JA
where T
A
is the ambient temperature and q
JA
is the MOSFET
junction to ambient thermal resistance.
Once you have T
J
, iterate your calculations recomputing
d, power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and efficiency.
The LT3837 gate drives will clamp the max gate voltage to
roughly 7.4V, so you can safely use MOSFETs with max
V
GS
of 10V or larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary side synchronous controllers available that
provide the buffer function as well as additional features.
Capacitor Selection
In a flyback converter, the input and output current flows in
pulses, placing severe demands on the input and output filter
capacitors. The input and output filter capacitors are selected
based on RMS current ratings and ripple voltage.
Select an input capacitor with a ripple current rating
greater than:
I
RMS
=
P
IN
V
IN(MIN)
1–DC
MAX
DC
MAX
Continuing the example:
I
RMS
=
37.5W
9V
1–52.4%
52.4%
= 3.97A
Input capacitor series resistance (ESR) and inductance
(ESL) need to be small as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater than:
I
RMS
=I
OUT
DC
MAX
1–DC
MAX
Continuing the example:
I
RMS
=10A
52.4%
1–52.4%
=10.5A
This is calculated for each output in a multiple winding
application.
LT3837
23
3837fd
APPLICATIONS INFORMATION
OUTPUT VOLTAGE
RIPPLE WAVEFORM
SECONDARY
CURRENT
PRIMARY
CURRENT
I
PRI
∆V
COUT
3825 F07
RINGING
DUE TO ESL
I
PRI
N
∆V
ESR
Figure 7. Typical Flyback Converter Waveforms
ESR and ESL along with bulk capacitance directly affect
the output voltage ripple. The waveforms for a typical
flyback converter are illustrated in Figure 7.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ∆V. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESR
COUT
≤1%•
V
OUT
• 1–DC
MAX
( )
I
OUT
The other 1% is due to the bulk C component, so use:
C
OUT
≥
I
OUT
1%• V
OUT
• f
OSC
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple, reli-
ability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
ESR
COUT
≤1%•
3.3V • 1–52.4%
( )
10A
=1.6mΩ
C
OUT
≥
10A
1%• 3.3• 200kHz
=1515µF
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to
use a simple LC filter. Figure 8 shows an example of the
filter.
R
LOAD
C
OUT2
1µF
V
OUT
C
OUT
470µF
C1
47µF
×3
FROM
SECONDARY
WINDING
L1
0.1µH
3837 F08
Figure 8
SwitcherCAD is a trademark of Linear Technology Corporation.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guide lines. Start with a C
OUT
1/4 the size of the nonfilter
solution. Make C1 1/4 of C
OUT
to make the second filter
pole independent of C
OUT
. The smaller C1 may be best
implemented with multiple ceramic capacitors. Make L1
smaller than the output inductance of the transformer. In
general, a 0.1µH filter inductor is sufficient. Add a small
ceramic capacitor (C
OUT2
) for high frequency noise on
V
OUT
. For those interested in more details refer to “Sec-
ond-Stage LC Filter Design,” Ridley, Switching Power
Magazine, July 2000, p8-10.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitics. LTC SwitcherCAD™ is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
LT3837
24
3837fd
APPLICATIONS INFORMATION
IC Thermal Considerations
Take care to ensure that the LT3837 junction temperature
does not exceed 125°C. Power is computed from the aver-
age supply current, the sum of quiescent supply current
(I
CC
in the specifications) plus gate drive currents.
The primary gate drive current is computed as:
f
OSC
• Q
G
where Q
G
is the total gate charge at max V
GS
(obtained from
the gate charge curve) and f is the switching frequency.
Since the synchronous driver is usually driving a capacitive
load, the power dissipation is:
f
OSC
• C
S
• V
SGMAX
where C
S
is the SG capacitive load and V
SGMAX
is the SG
pin max voltage.
So total IC dissipation is computed as:
P
D(TOTAL)
= V
CC
• (I
CC
+ f •(Q
GPRI
+ C
S
• V
SGMAX
))
V
CC
is the worst-case LT3837 supply voltage.
Junction temperature is computed as:
T
J
= T
A
+ P
D
• q
JA
where:
T
A
is the ambient temperature
q
JA
is the FE16 package junction-to-ambient thermal
impedance (40°C/W).
PC Board Layout Considerations
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LT3837 directly
to the ground terminal of the V
CC
decoupling capacitor,
the bottom terminal of the current sense resistor, the
ground terminal of the input capacitor, and the ground
plane (multiple vias). Place the V
CC
capacitor immediately
adjacent to the V
CC
and GND pins on the IC package.
This capacitor carries high di/dt MOSFET gate drive cur-
rents. Use a low ESR ceramic capacitor.
Take care in PCB layout to keep the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
also minimizes magnetic field radiation. Figure 9 outlines
the critical paths.
Keep electric field radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
Check that the maximum BV
DSS
ratings of the MOSFETs
are not exceeded due to inductive ringing. This is done by
viewing the MOSFET node voltages with an oscilloscope. If
it is breaking down either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
Place the small-signal components away from high fre-
quency switching nodes. This allows the use of a pseudo-
Kelvin connection for the signal ground, where high di/dt
gate driver currents flow out of the IC ground pin in one
direction (to the bottom plate of the V
CC
decoupling
capacitor) and small-signal currents flow in the other
direction.
Keep the trace from the feedback divider tap to the FB
short to preclude inadvertent pickup.
For applications with multiple switching power converters
connected to the same input supply, make sure that the
input filter capacitor for the LTC3837 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple and this could
interfere with the LT3837 operation. A few inches of PC
trace or wire (L @ 100nH) between the C
IN
of the LT3837
and the actual source V
IN
is sufficient to prevent current
sharing problems.
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LT3837EFE#TRPBF

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Buy LT3837EFE#TRPBF
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Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Iso No-Opto Sync Fly Cntr
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