MPC7448 Hardware Specifications Addendum for the MC7448xxnnnnNx Series, Rev. 6
Freescale Semiconductor 7
General Parameters
5.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications for the MPC7448 part numbers discussed here.
NOTE
The core frequency information in this table applies when the device
operates at the nominal core voltage indicated in Table 4. For core
frequency specifications at derated core voltage conditions, see Section 5.3,
“Voltage and Frequency Derating.”
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Ta bl e 4 .
Characteristic Symbol
Maximum Processor Core Frequency (MHz)
Unit Notes600 667 800 867 1000 1250 1267 1400
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Processor
frequency
DFS mode
disabled
f
core
500 600 500 667 500 800 500 867 500 1000 500 1250 500 1267 500 1400 MHz
1, 8, 9
Processor
frequency
DFS mode
enabled
f
core
_
DFS
250 300 250 333 250 400 250 433 250 500 250 625 250 633 250 700 MHz
10
VCO
frequency
f
VCO
500 600 500 667 500 800 500 867 500 1000 500 1250 500 1267 500 1400 MHz
1, 9
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus) frequency,
processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:5] signal description in Section 9.1.1, “PLL Configuration,” in the hardware specifications for valid
PLL_CFG[0:5] settings.
8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled.
f
core_DFS
provides the maximum and minimum core frequencies in a DFS mode.
9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at the nominal
core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies must be reduced. See
Section 5.3, “Voltage and Frequency Derating,” for more information.
10.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes
(divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum
frequencies stated for f
core
.