LTC1658IMS8#TRPBF

4
LTC1658
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: DAC switched between code 16383 and code 50.
Note 4: Digital inputs at 0V or V
CC
.
Note 5: V
OUT
can only swing from (GND + V
OS
) to (V
CC
V
OS
) when
output is unloaded. See Applications Information.
Note 6: Guaranteed by design. Not subject to test.
Note 7: Measured at code 50.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Differential Nonlinearity (DNL) vs
Input Code
Supply Current vs Logic Input
Voltage
CODE
0
–5
–1
–2
–3
–4
0
1
2
3
4
5
INL ERROR (LSB)
4096 8192
1658 G01
12288
16383
Integral Nonlinearity (INL) vs
Input Code
LOGIC INPUT VOLTAGE (V)
012345
SUPPLY CURRENT (mA)
1658 G03
3
2
1
0
ALL DIGITAL INPUTS
TIED TOGETHER
CODE
0
1.0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
1.0
DNL ERROR (LSB)
4096 8192
1658 G02
12288
16383
Minimum Output Voltage vs
Output Sink Current Offset Error vs Temperature
Minimum Supply Headroom for
Full Output Swing vs Load Current
OUTPUT SINK CURRENT (mA)
0 5 10 15
OUTPUT PULL-DOWN VOLTAGE (V)
1658 G05
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CODE: ALL ZEROS
125°C
25°C
–55°C
LOAD CURRENT (mA)
0 5 10 15
V
CC
– V
OUT
(V)
1658 G04
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
OUT
< 1LSB
CODE: ALL 1s
V
OUT
= 4.096V
125°C
25°C
–55°C
TEMPERATURE (°C)
–55 –25 5 35 65 95 125
OFFSET ERROR (LSB)
1658 G06
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5
LTC1658
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Broadband Noise
TEMPERATURE (°C)
–55 –25 5 35 65 95 125
GAIN ERROR (LSB)
1658 G06
5
4
3
2
1
0
–1
–2
–3
–4
–5
Gain Error vs Temperature
BW = 1Hz TO 200µs/DIV 1658 G08
100kHz
PIN FUNCTIONS
UUU
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D
IN
(Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the D
IN
pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1658 requires a 16-bit word to be loaded in.
The last two bits are don’t cares.
CS/LD (Pin 3): The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
OUT
(Pin 4): Output of the Shift Register Which Becomes
Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
REF (Pin 6): Reference Input. There is a gain of one from
this pin to the output. When tied to V
CC
the output will
swing from GND to V
CC
. The output can only swing to
within it’s offset specification of V
CC
(see Applicatons
Information).
V
OUT
(Pin 7): Buffered Rail-to-Rail DAC Output.
V
CC
(Pin 8): Positive Supply Input. 2.7V V
CC
5.5V.
1LSB/DIV
6
LTC1658
TI I G DIAGRA
WU W
B12
B13
MSB
t
1
t
6
t
9
BX
DUMMY
BX
DUMMY
B0
LSB
B11
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1658 TD
B13
PREVIOUS WORD
B13
CURRENT WORD
B11B12 BX
BX
DEFI ITIO S
UU
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (V
OUT
– LSB)/LSB
Where V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Gain Error: Gain error is the difference between the output
of a DAC from its ideal full-scale value after offset error has
been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is
calculated
as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/16383)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
REF
/16384
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.

LTC1658IMS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 14-bit Micropower DAC in MSOP Package
Lifecycle:
New from this manufacturer.
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