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ADM6819ARJZ-REEL7

P1-P3P4-P6P7-P9P10-P12
FET Drive Simple Sequencers
®
ADM6819/ADM6820
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Single chip enables power supply sequencing of two
supplies
On-board charge pump fully enhances N-channel FET
Adjustable primary supply monitor to 0.618 V
Delay from primary supply to secondary supply enabled
Fixed 300 ms delay (ADM6819)
Capacitor adjustable delay (ADM6820)
Logic/analog driven enable input (ADM6819)
−40°C to +85°C operating range
Packaged in small 6-lead SOT-23 package
Pin-to-pin compatibility with MAX6819/MAX6820
APPLICATIONS
Multivoltage systems
Dual voltage microprocessors/FPGAs/ASICs/DSPs
Network processors
Telecom and datacom systems
PC/server applications
FUNCTIONAL BLOCK DIAGRAM
V
CC2
V
CC2
OUT
Q1
GATE
LOGIC
V
CC2
V
FET
SETV
EN (ADM6819) - DIGITAL/ANALOG
SETD (ADM6820)
0.618V
0.618V
GND
R1
R2
V
CC1
ADM6819/
ADM6820
V
CC1
V
CC1
FET
DRIVER
CHARGE
PUMP
TIMER
UVLO
0
5133-001
Figure 1.
GENERAL DESCRIPTION
The ADM6819 and ADM6820 are simple power supply sequencers
with FET drive capability for enhancing N-channel MOSFETs.
These devices can monitor a primary supply voltage and
enable/disable an external N-channel FET for a secondary
supply. The ADM6819 has the ability to monitor two supplies.
When more than two voltages require sequencing, multiple
ADM6819/ADM6820 devices can be cascaded to achieve this.
The devices operate over a supply range of 2.95 V to 5.5 V.
An internal comparator monitors the primary supply using the
VSET pin. The input to this comparator is externally set via a
resistor divider from the primary supply. When the voltage at
the VSET pin rises above the comparator threshold, an internal
charge pump on the GATE output enhances the secondary
supply FET.
The ADM6819 features an enable (EN) pin that is fed to the
input of an additional comparator and reference circuit. This
pin can be used as a digital enable or a secondary power good
comparator to monitor a second supply and enables the GATE
only if both supplies are valid. When both inputs of the internal
comparators are above the threshold, a fixed 300 ms timeout
occurs before the GATE is driven high and the secondary
supply is enabled.
The ADM6820 has only one comparator that is on the SETV
pin. It also features a timeout period that is adjustable via a
single external capacitor on the SETD pin.
The ADM6819/ADM6820 are packaged in small 6-lead SOT-23
packages.
ADM6819/ADM6820
Rev. 0 | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.............................................................................. 4
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 10
SETV Pin ..................................................................................... 10
EN Pin.......................................................................................... 10
GATE Pin .................................................................................... 10
SETD Pin..................................................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
7/06—Rev. 0: Initial Version
ADM6819/ADM6820
Rev. 0 | Page 3 of 12
SPECIFICATIONS
V
CC1
or V
CC2
= 2.95 V to 5.5 V, T
A
= −40°C to +85°C, unless otherwise noted. Typical values are at T
A
= 25°C.
1
Table 1.
Parameter Min Typ Max Units Conditions
V
CC1
, V
CC2
PINS V
CC1
or V
CC2
must be > 2.95 V
Operating Voltage Range, V
CC1
or V
CC2
0.9 5.5 V V
CC1
or V
CC2
must be > 2.95 V
V
CC1
or V
CC2
Supply Current, I
CC
350 500 μA V
CC1
= V
CC2
= 3.3 V
V
CC1
or V
CC2
Disable Mode Current 250 μA V
CC1
= V
CC2
= 3.3 V, EN = GND
V
CC1
or V
CC2
Slew Rate
2
6 V/s ADM6819
1.2/t
DELAY
V/s ADM6820
3
Undervoltage Lockout, V
UVLO
2.4 2.525 2.65 V V
CC
falling
SETV PIN
SETV Threshold, V
TH
0.602 0.618 0.634 V V
SETV
rising, enables GATE
SETV Input Current
2
10 100 nA
SETV Threshold Hysteresis
−1 % V
SETV
falling, disables GATE
SETV to GATE Delay, t
DELAY
240 300 350 ms V
SETV
> V
TH
; V
EN
> V
TH
(ADM6819)
SETD PIN ADM6820
SETD Ramp Current, I
SETD
300 500 730 nA
400 500 600 nA T
A
= 25°C
SETD Voltage, V
SETD
1.295 1.326 1.357 V
GATE PIN
GATE Turn-On Time, t
ON
0.5 1.5 10 ms C
GATE
= 1500 pF, V
CC2
= 3.3 V, V
GATE
= 7.8 V
GATE Turn-Off Time, t
OFF
30 μs C
GATE
= 1500 pF, V
CC2
= 3.3 V, V
GATE
= 0.5 V
GATE Voltage, V
GATE
4.5 5.5 6.0 V With respect to V
CCx
, R
GATE
> 50 MΩ to V
CCx
4
4.0 5.0 6 V With respect to V
CCx
, R
GATE
> 5 MΩ to V
CCx
4
8.9 9.4 9.9 V With respect to V
CCx
, R
GATE
> 50 MΩ to V
CCx
5
8.2 8.6 9.1 V With respect to V
CCx
, R
GATE
> 5 MΩ to V
CCx
5
ENABLE PIN
EN Input Voltage Low, V
IL
0.4 V V
CC1
or V
CC2
must be > 2.95 V
EN Input Voltage High, V
IH
2.0 V V
CC1
or V
CC2
must be > 2.95 V
1
100% production tested at T
A
= +25°C. Specifications over temperature limit are guaranteed by design.
2
Guaranteed by design, not production tested.
3
t
DELAY
(s) = 2.65 × 10
6
× C
SET
.
4
Highest supply pin is represented by V
CCx
= 2.95 V.
5
Highest supply pin is represented by V
CCx
= 5.5 V.
P1-P3P4-P6P7-P9P10-P12

ADM6819ARJZ-REEL7

Mfr. #:
Buy ADM6819ARJZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits FET Drive w/ Fixed 200ms Delay
Lifecycle:
New from this manufacturer.
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