ADM6819/ADM6820
Rev. 0 | Page 7 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
CC1
1
GND
2
ET
3
V
CC2
6
GATE
5
EN
4
ADM6819
TOP VIEW
(Not to Scale)
05133-002
Figure 6. ADM6819 Pin Configuration
V
CC1
1
GND
2
ET
3
V
CC2
6
GATE
5
SETD
4
05133-003
ADM6820
TOP VIEW
(Not to Scale)
Figure 7. ADM6820 Pin Configuration
Table 4. Pin Function Descriptions
Pin Number
ADM6819 ADM6820
Mnemonic Description
1 1 V
CC1
Supply Voltage 1. Either V
CC1
or V
CC2
must be greater than the UVLO to enable external
FET Drive.
2 2 GND Chip Ground Pin.
3 3 SETV
Sequenced Threshold Set. Connect to an external resistor divider to set the V
CC1
threshold that enables GATE turn-on. The internal reference is 0.618 V.
4 – EN
Active-High Enable. GATE drive is enabled t
DELAY
after EN is driven high. GATE drive is
immediately disabled when EN is driven low. Connect this pin to the higher of V
CC1
or
V
CC2
if not used. EN is internally identical to SETV (0.618 V threshold) and, therefore, can
be used as a second supply monitor, enabling two supplies to be validated before
sequencing begins.
– 4 SETD
GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust the
delay from SETV > V
TH
to GATE turn-on. t
DELAY
(s) = 2.652 × 10
6
× C
SET
(F).
5 5 GATE
GATE Drive Output. GATE drives an external N-channel FET to connect V
CC2
to the load.
GATE drive enables t
DELAY
after SETV exceeds V
TH
and ENABLE is driven high. GATE drive is
immediately disabled when SETV drops below V
TH
or ENABLE is driven low. When
enabled, an internal charge pump drives GATE above V
CCX
to fully enhance the external
N-channel FET.
6 6 V
CC2
Supply Voltage 2. Either V
CC1
or V
CC2
must be greater than the UVLO to enable the
external FET Drive.
