MAX4950CTO+T

MAX4950
Quad PCI Express Equalizer/Redriver
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN NAME FUNCTION
32 OUT1N Inverting Output 1
33 OUT1P Noninverting Output 1
35 OUT0N Inverting Output 0
36 OUT0P Noninverting Output 0
39 EN
Enable Input. Drive EN low for standby mode. Drive EN high for normal mode. EN is internally
pulled down by 60k (typ) resistor.
40 RX_DET
Receiver Detection Control Bit. Drive RX_DET high to initiate receiver detection. Drive RX_DET low
for normal mode. RX_DET is internally pulled down by 60k (typ) resistor.
41 O_AMP Output Redrive Selection Input. O_AMP is internally pulled down by 60k (typ) resistor.
42 P_SAV Power-Save Mode Input. P_SAV is internally pulled down by 60k (typ) resistor. See Table 6.
—EP
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to maximize
thermal performance. EP is not intended as an electrical connection point.
MAX4950
EQUALIZER
EQUALIZER
R
HI
GLOBAL
POWER SAVE
ELECTRICAL IDLE
DETECTOR
RECEIVER DETECT
MANAGER
OUTPUT
ENABLE
EN
RX_DET
P_SAV O_AMP
OEQ0
OEQ1
OUT_P
OUT_N
IN_P
INEQ1
INEQ0
IN_N
Functional Diagram
MAX4950
Quad PCI Express Equalizer/Redriver
8 _______________________________________________________________________________________
Detailed Description
The MAX4950 quad equalizer/redriver is designed to
support both Gen I (2.5GT/s) and Gen II (5.0GT/s) PCIe
data rates. The device contains four identical drivers
with idle/receive detect on each lane and equalization to
compensate for circuit-board loss. Signal integrity at the
receiver is improved by the use of programmable input
equalization circuitry. The MAX4950 output features a
redrive output swing selection input, O_AMP (Table 1),
and programmable output deemphasis, permitting opti-
mal placement of key PCIe components and longer runs
of stripline, microstrip, or cable.
Programmable Input Equalization
The MAX4950 features a programmable input equalizer
capable of providing 0dB, 3.5dB, or 6dB of high-fre-
quency boost by setting 2 control bits, INEQ1 and
INEQ0 (see Table 2).
Programmable Output Deemphasis
The MAX4950 features programmable output deempha-
sis by setting two control bits, OEQ1 and OEQ0, for de-
emphasis ratios of 0dB, 3.5dB, and 6dB (see Table 3).
Receiver Detection
The MAX4950 features receiver detection on each chan-
nel. Upon initial power-up, if EN is high, receiver detec-
tion initializes. Receiver detection can also be initiated
on a rising edge of the RX_DET input when EN is high.
During this time, the part remains in low-power standby
mode and the outputs are disabled, despite the logic-
high state of EN. Until a channel has detected a receiv-
er, receiver detection repeats indefinitely on each
channel. If a channel detects a receiver, the other chan-
nels are limited to three retries. Upon receiver detection,
channel output and electrical idle detection are enabled.
Note: With a slowly rising power supply, it is recom-
mended to toggle EN to avoid potential receiver detec-
tion timeout conditions.
Electrical Idle Detection
The MAX4950 features electrical idle detection to prevent
unwanted noise from being redriven at the output. If the
MAX4950 detects that the differential input has fallen
below V
TX-IDLE-THRESH
, the MAX4950 squelches the out-
put. For differential input signals that are above
V
TX-IDLE-THRESH
, the MAX4950 turns on the output and
redrives the signal. There is little variation in output
common-mode voltage between electrical idle and
redrive modes.
Power-Saving Features
The MAX4950 features a power-save mode to reduce
quiescent supply current. In power-save mode, electri-
cal idle and receiver detection circuitry for channels 1,
2, and 3 are turned off, and all channel operation is
slaved to channel 0. This feature is useful for reducing
power consumption in applications where all channels
operate simultaneously. During normal operation, all
channels have independent electrical idle and receiver
detection. Drive P_SAV high to activate power-save
mode; drive P_SAV low for normal operation. To further
reduce power consumption, the MAX4950 features a
standby input (EN) when the device is not needed. To
place the device in standby mode, drive EN low. To
enable the device, drive EN high. Table 5 shows typical
power consumption differences between normal mode,
power-save mode, and standby mode with different
output redrive strengths.
INEQ1 INEQ0 INPUT EQUALIZATION (dB)
0 0 0 at 5.0GT/s
0 1 3.5 (typ) at 5.0GT/s
1 X 6 (typ) at 5.0GT/s
Table 2. Input Equalization
X = Don’t Care.
OEQ1 OEQ0 OUTPUT DEEMPHASIS RATIO (dB)
0 0 0 at 5.0GT/s
0 1 3.5 (typ) at 5.0GT/s
1 X 6 (typ) at 5.0GT/s
Table 3. Output Deemphasis
X = Don’t Care.
O_AMP DIFFERENTIAL OUTPUT VOLTAGE (mV
P-P
)
0 1000 (typ)
1 750 (typ)
Table 1. Output Redrive Swing
RX_DET EN DESCRIPTION
X 0 Receiver Detection Inactive
0 1 Receiver Detection Inactive
Rising
Edge
1 Initiate Receiver Detection
11
Following a Rising Edge, Indefinite
Retry Until Receiver Detected
Table 4. Receiver Detection Input Function
X = Don’t Care.
MAX4950
Quad PCI Express Equalizer/Redriver
_______________________________________________________________________________________ 9
Applications Information
Figure 2 shows a typical application with two
MAX4950s, both residing on the main board, with input
and output equalization set individually for optimal per-
formance. The receive equalizer is set to receive a
degraded signal coming from a remote board through
two sets of connectors, and a midplane stripline trans-
mission. The output of the Rx section has little or no out-
put equalization. The Tx section takes a high-quality
signal, and provides boost to the output (deemphasis).
Layout
Circuit-board layout and design can significantly affect
the performance of the MAX4950. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using controlled-impedance
transmission lines on data signals. Power-supply
decoupling should also be placed as close to V
CC
as
possible. Always connect V
CC
to a power plane. It is
recommended to run receive and transmit on different
layers to minimize crosstalk.
Exposed-Pad Package
The exposed-pad, 42-pin TQFN package incorporates
features that provide a very low thermal-resistance path
for heat removal from the IC. The exposed pad on the
MAX4950 must be soldered to the circuit-board ground
plane for proper thermal performance. For more infor-
mation on exposed-pad packages, refer to Maxim
Application Note HFAN-08.1:
Thermal Considerations of
QFN and Other Exposed-Paddle Packages
.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all devices. Always apply GND then V
CC
before apply-
ing signals, especially if the signal is not current limited.
Chip Information
PROCESS: BiCMOS
EN P_SAV O_AMP
QUIESCENT POWER
SUPPLY CURRENT
(typ) (mA)
QUIESCENT POWER
SUPPLY CURRENT
(max) (mA)
QUIESCENT POWER
DISSIPATION
(3.3V, typ) (mW)
QUIESCENT POWER
DISSIPATION
(3.6V, max) (mW)
0 0 0 100 125 330 450
0 0 1 80 100 264 360
0 1 0 100 125 330 450
0 1 1 80 100 264 360
1 0 0 262 328 865 1181
1 0 1 242 303 799 1091
1 1 0 214 268 706 965
1 1 1 194 243 640 875
Table 5. Power-Save Mode Quiescent Power Dissipation
4 DIFFERENTIAL PAIRS
Rx
Tx
MIDPLANE
REMOTE BOARD
4 DIFFERENTIAL PAIRS
CONNECTORS
MAX4950
PCIe
Tx
Rx
MAIN BOARD
PCIe
MAX4950
Figure 2. Typical Application Diagram

MAX4950CTO+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - Signal Buffers, Repeaters Quad PCI Express Equalizer/Re-Driver
Lifecycle:
New from this manufacturer.
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