AD678
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6
PIN DESCRIPTION
28-Lead DIP 44-Lead
Symbol Pin No. JLCC Pin No. Type Name and Function
AGND 7 11 P Analog Ground. This is the ground return for AIN only.
AIN 6 10 AI Analog Signal Input.
BIPOFF 10 15 AI Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary
output coding. Connect to REF
OUT
through 50 resistor for ± 5 V input bipolar mode
and twos complement binary output coding. See Figures 7 and 8.
CS 4 6 DI Chip Select. Active LOW.
DGND 14 23 P Digital Ground
DB11–DB4 26–19 40, 39, 37, 36, DO Data Bits 11 through 4. In 12-bit format (see 12/8 pin), these pins provide the upper 8 bits
35, 34, 33, 31 of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/L pin).
Active HIGH.
DB3, DB2 18, 17 30, 27 DO Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.
Active HIGH. In 8-bit format they are undefined and should be tied to V
DD
.
DB1 (R/L) 16 26 DO In 12-bit format, Data Bit 1. Active HIGH.
DB0 (HBE) 15 25 DO In 12-bit format, Data Bit 0. Active HIGH.
EOC 27 42 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the
conversion is finished. In asynchronous mode, EOC is an open drain output and
requires an external 3 k pull-up resistor. See EOCEN and SYNC pins for information
on EOC gating.
EOCEN 1 1 DI End-Of-Convert Enable. Enables EOC pin. Active LOW.
HBE (DB0) 15 25 DI In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte.
OE 2 3 DI Output Enable. The falling edge of OE enables DB11–DB0 in 12-bit format and
DB11–DB4 in 8-bit format. Gated with CS. Active LOW.
REF
IN
9 14 AI Reference Input. +5 V input gives 10 V full-scale range.
REF
OUT
8 12 AO +5 V Reference Output. Tied to REF
IN
through 50 resistor for normal operation.
R/L (DB1) 16 26 DI In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.
Tied to V
DD
for right-justified output and tied to DGND for left-justified output.
SC 3 5 DI Start Convert. Active LOW. See SYNC pin for gating.
SYNC 13 21 DI SYNC Control. If tied to V
DD
(synchronous mode), SC, EOC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,
and EOC is an open drain output. EOC requires an external 3 k pull-up resistor in
asynchronous mode.
V
CC
11 17 P +12 V Analog Power.
V
EE
5 8 P –12 V Analog Power.
V
DD
28 43 P +5 V Digital Power.
12/8 12 19 DI Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied
LOW, sets output format to 8-bit multiplexed.
No Connect 2, 4, 7, 9, 13, These pins are unused and should be connected to DGND or V
DD
.
16, 18, 20, 22,
24, 28, 29, 32,
38, 41, 44
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers; P = Power.
PIN CONFIGURATIONS
DIP PACKAGE JLCC PACKAGE
EOCEN
OE
V
EE
AIN
AGND
SC
CS
REF
OUT
REF
IN
BIPOFF
V
CC
12/8
SYNC
DGND
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
8
21
920
10 19
11
12 17
16
14
15
TOP VIEW
(Not to Scale)
AD678
V
DD
EOC
DB9
DB8
DB7
DB11
DB10
DB6
DB5
DB4
DB3
DB2
DB1 (R/L)
DB0 (HBE)
6 5 4 3 2 44 43 42 41 40
18 19 20 21 22 24 25 26 27 2823
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PIN 1
IDENTIFIER
TOP VIEW
NC
NC
NC
NC
V
EE
AIN
AGND
REF
OUT
REF
IN
BIPOFF
V
CC
NC
NC
NC
DB9
DB8
DB7
DB10
DB6
DB5
DB4
DB3
CS
SC
NC
OE
NC
EOCEN
V
DD
EOC
DB11
NC
NC
NC
NC
DGND
NC
NC
12/8
SYNC
DB0 (HBE)
DB1 (R/L)
DB2
NC
AD678
NC = NO CONNECT
Definition of SpecificationsAD678
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of
the measured input sides to the rms sum of the distortion terms.
The two signals applied to the converter are of equal ampli-
tude and the peak value of their sum is –0.5 dB from full scale
(9.44 V p-p). The IMD products are normalized to a 0 dB
input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than 0.1 dB. Beyond this frequency, distor-
tion of the sampled input signal increases significantly.
The AD678 has been designed to optimize input bandwidth, al-
lowing the AD678 to undersample input signals with frequen-
cies significantly above the converter’s Nyquist frequency.
APERTURE DELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aper-
ture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INPUT SETTLING TIME
Settling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes (NMC) are guaranteed.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level 1/2
LSB above analog ground. Unipolar zero error is the deviation
of the actual transition from that point. This error can be ad-
justed as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (1111 1111
1111 to 0000 0000 0000) should occur at an analog value 1/2
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9963 volts for a 0–10 V range,
4.9963 volts for a ±5 V range). The gain error is the deviation of
the actual difference between the first and last code transition
from the ideal difference between the first and last code transi-
tion. This error can be adjusted as shown in the Input Connec-
tions and Calibration section.
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition. Integral nonlinearity is the worst-case deviation of a code
from the straight line. The deviation of each code is measured
from the middle of that code.
POWER SUPPLY REJECTION
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
TEMPERATURE DRIFT
This is the maximum change in the parameter from the initial
value (@ +25°C) to the value at T
MIN
or T
MAX
.
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7
Figure 4. Harmonic Distortion vs. Input Frequency
Figure 5. S/N+D vs. Input Amplitude
(f
SAMPLE
200 kSPS)
Figure 6. S/N+D vs. Input Frequency and Amplitude
AD678Dynamic Performance
Figure 7. Nonaveraged 2048 Point FFT at 200 kSPS,
f
IN
= 49.902 kHz
Figure 8. IMD Plot for f
IN
= 9.08 kHz (fa), 9.58 kHz (fb)
Figure 9. Power Supply Rejection (f
IN
= 10 kHz,
f
SAMPLE
= 200 kSPS, V
RIPPLE
= 0.1 V p-p)
8
REV. C

AD678SD/883B

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 12-BIT 200 kSPS Complete SAMPLING
Lifecycle:
New from this manufacturer.
Delivery:
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