OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

IS62WV25616BLL-55TI-TR

P1-P3P4-P6P7-P9P10-P12P13-P14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CS1 = OE = VIl, WE = VIh, UB or LB = VIl)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1
t
LZCE1
t
HZOE
HIGH-Z
DATA VALID
t
HZCS1
ADDRESS
OE
CS1
DOUT
LB
,
UB
t
HZB
t
BA
t
LZB
READ CYCLE NO. 2
(1,3)
(CS1, OE,ANDUB/LB Controlled)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CS1, UB, or LB =
VIl. WE=VIh.
3. Address is valid prior to or coincident with CS1LOWtransition.
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
55 ns
70 ns
Symbol Parameter Min. Max. Min. Max. Unit
twc WriteCycleTime 55 — 70 — ns
tscs1 CS1 to Write End 45 — 60 — ns
taw AddressSetupTimetoWriteEnd 45 — 60 — ns
tha AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwb LB, UB Valid to End of Write 45 — 60 — ns
tPwe WE Pulse Width 40 — 50 — ns
tsd DataSetuptoWriteEnd 25 — 30 — ns
thd DataHoldfromWriteEnd 0 — 0 — ns
thzwe
(3)
WELOWtoHigh-ZOutput — 20 — 20 ns
tlzwe
(3)
WEHIGHtoLow-ZOutput 5 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4Vto
V
dd-0.2V/Vdd-0.3VandoutputloadingspeciedinFigure1.
2.
TheinternalwritetimeisdenedbytheoverlapofCS1LOWandUB or LB, and WELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyone
can go inactive to
terminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. F
08/25/2014
IS62WV25616ALL, IS62WV25616BLL
WRITE CYCLE NO. 2 (WE Controlled: OEisHIGHDuringWriteCycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
WE
LB, UB
DOUT
DIN
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1 and WE inputs and at
least one of the LB and UBinputsbeingintheLOWstate.
2. WRITE=(CS1) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1 Controlled, OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
LB, UB
t
PWB
P1-P3P4-P6P7-P9P10-P12P13-P14

IS62WV25616BLL-55TI-TR

Mfr. #:
Buy IS62WV25616BLL-55TI-TR
Manufacturer:
ISSI
Description:
SRAM 4Mb 256Kx16 55ns Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet