OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

74SSTVF16857PAG8

P1-P3P4-P6
1
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
JUNE 2003
2003 Integrated Device Technology, Inc. DSC-6198/8c
IDT74SSTVF16857
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
14-BIT REGISTERED
BUFFER WITH SSTL I/O
DESCRIPTION:
The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V
VDD and supports low standby operation. All data inputs and outputs are
SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of RESET.
FEATURES:
• 2.3V to 2.7V Operation
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
34
38
39
35
48
R
1D
C1
1
Q1
RESET
CLK
CLK
VREF
D1
TO 13 OTHER CHANNELS
2
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
PIN CONFIGURATION
TSSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max. Unit
VDD or VDDQ Supply Voltage Range –0.5 to 3.6 V
VI
(2)
Input Voltage Range –0.5 to VDD +0.5 V
VO
(3)
Output Voltage Range –0.5 to VDDQ +0.5 V
IIK Input Clamp Current, VI < 0 –50 mA
I
OK Output Clamp Current, ±50 mA
VO < 0 or VO > VDDQ
IO Continuous Output Current, ±50 mA
VO = 0 to VDDQ
VDD Continuous Current through each ±100 mA
VDD, VDDQ or GND
T
STG Storage Temperature Range –65 to +150 ° C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) VO = VDDQ
FUNCTION TABLE
(1)
Input
RESET CLK CLK D Q Outputs
H ↑↓ LL
H ↑↓ HH
H L or H L or H X Qo
(2)
LX X X L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2. Qo = Output level before the indicated steady-state conditions were established.
481
Q
1 D1
247Q2
D2
GND
346GND
V
DDQ 445
V
DD
5
44Q
3
D3
643Q4
D4
742Q5
D5
GND
841D
6
VDDQ 9
40
D7
10 39Q6 CLK
11 38Q7
CLK
12 37
V
DDVDDQ
GND 13 36
GND
14 35
Q
8
VREF
15
34Q
9
RESET
16 33VDDQ
D8
17 32
GND
D9
18
31
Q10 D10
19 30Q11
D11
20 29Q12
D12
21 28
V
DD
VDDQ
22
27
GND GND
23 26
Q
13
D13
24 25
Q
14
D14
3
COMMERCIAL TEMPERATURE RANGE
IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIK Control Inputs VDD = 2.3V, II = −18mA — — –1.2 V
V
OH VDD = 2.3V to 2.7V, IOH = -100μAVDD – 0.2 — — V
VDD = 2.3V, IOH = -8mA 1.95 — —
VOL VDD = 2.3V to 2.7V, IOL = 100μA — — 0.2 V
VDD = 2.3V, IOL = 8mA — — 0.35
II All Inputs VDD = 2.7V, VI = VDD or GND — — ±5 μA
IDD Static Standby IO = 0, VDD = 2.7V, RESET = GND — — 0.01 mA
Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) —6—
I
DDD Dynamic Operating (Clock Only) IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),———μA/Clock
CLK and CLK Switching 50% Duty Cycle. MHz
Dynamic Operating I
O = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),———μA/Clock
(Per Each Data Input) CLK and CLK Switching 50% Duty Cycle. One Data Input MHz/Data
Switching at Half Clock Frequency, 50% Duty Cycle. Input
Data Inputs V
DD = 2.5V, VI = VREF ± 310mV 2.5 — 3.5
C
I CLK and CLK VICR = 1.25V, VI (PP) = 360mV 2.5 — 3.5 pF
RESET VI = VDD or GND — — —
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V
OPERATING CHARACTERISTICS, TA = 25ºC
(1)
Symbol Parameter Min. Typ.
(1)
Max. Unit
VDD Supply Voltage VDDQ — 2.7 V
VDDQ Output Supply Voltage 2.3 2.5 2.7 V
VREF Reference Voltage (VREF= VDDQ/2) 1.15 1.25 1.35 V
VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V
VI Input Voltage 0 — VDD V
VIH AC High-Level Input Voltage Data Inputs VREF+ 310mV — — V
VIL AC Low-Level Input Voltage Data Inputs — — VREF– 310mV V
VIH DC High-Level Input Voltage Data Inputs VREF+ 150mV — — V
VIL DC Low-Level Input Voltage Data Inputs — — VREF– 150mV V
VIH High-Level Input Voltage RESET 1.7 — — V
VIL Low-Level Input Voltage RESET — — 0.7 V
VICR Common-Mode Input Range CLK, CLK 0.97 — 1.53 V
VI (PP) Peak-to-Peak Input Voltage CLK, CLK 360 — — mV
IOH High-Level Output Current — — – 20 mA
IOL Low-Level Output Current — — 20
TA Operating Free-Air Temperature 0 — +70 ° C
NOTE:
1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.
P1-P3P4-P6

74SSTVF16857PAG8

Mfr. #:
Buy 74SSTVF16857PAG8
Manufacturer:
IDT
Description:
Registers 14BIT REGIST BUFFER, SSTL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet