OMO ElectronicOMO Electronic
Expand menu
0 Cart

WM8532CGEFL/RV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
WM8532 Production Data
w
PD, Rev 4.2, June 2014
10
POWER ON RESET CIRCUIT
Figure 3 Internal Power on Reset Circuit Schematic
The WM8532 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is
used to reset the DAC digital logic into a default state after power up. The POR circuit is
powered by AVDD and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or
LINEVDD are below a minimum threshold.
Figure 4 Typical Power Timing Requirements
Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When
AVDD goes above the minimum threshold, V
pora
, there is enough voltage for the circuit to
guarantee POR is asserted low and the chip is held in reset. In this condition, all digital inputs
to the hardware control interface are ignored. After VMID rises to V
pord_hi
and AVDD rises to
V
pora_hi,
POR is released high and access to the control interface and audio interface may take
place. This assumes that DBVDD is at a level within the recommended operating conditions.
Production Data WM8532
w
PD, Rev 4.2, June 2014
11
On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the
minimum threshold V
pora_low
.
Test Conditions
LINEVDD = AVDD = DBVDD = 3.3V AGND = LINEGND = 0V, T
A
= +25
o
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Input Timing Information
VDD level to POR defined
(LINEVDD/AVDD rising)
V
pora
Measured from LINEGND 158 mV
VDD level to POR rising edge
(VMID rising)
V
pord_hi
Measured from LINEGND 0.63 0.8 1 V
VDD level to POR rising edge
(LINEVDD/AVDD rising)
V
pora_hi
Measured from LINEGND 1.44 1.8 2.18 V
VDD level to POR falling edge
(LINEVDD/AVDD falling)
V
pora_lo
Measured from LINEGND 0.96 1.46 1.97 V
Table 2 Power on Reset
Note: All values are simulated results
WM8532 Production Data
w
PD, Rev 4.2, June 2014
12
DEVICE DESCRIPTION
INTRODUCTION
The WM8532 provides high fidelity, selectable 1V
RMS
or 2V
RMS
ground referenced stereo line
output from a single supply line with minimal external components. The integrated DC servo
eliminates the requirement for external mute circuitry by minimising DC transients at the
output during power up/down. The device is well-suited to both stereo and multi-channel
systems.
The device supports all common audio sampling rates between 8kHz and 192kHz using
common MCLK fs rates, with a slave mode audio interface.
The WM8532 supports a simple hardware control mode, allowing access to 24-bit LJ and I
2
S
audio interface formats, mute control, de-emphasis filter and output level select. An internal
audio interface clock monitor automatically mutes the DAC output if the BCLK is interrupted.
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting audio data to the WM8532. The digital audio
interface uses three pins:
DACDAT: DAC data input
LRCLK: Left/Right data alignment clock
BCLK: Bit clock, for synchronisation
The WM8532 digital audio interface operates as a slave as shown in Figure 5.
Figure 5 Slave Mode
INTERFACE FORMATS
The WM8532 supports two different audio data formats:
Left justified
I
2
S
Both of these modes are MSB first. They are described in Audio Data Formats on page 13.
Refer to the “Electrical Characteristics” section for timing information.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

WM8532CGEFL/RV

Mfr. #:
Buy WM8532CGEFL/RV
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC, 2Vrms
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet