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WM8532CGEFL/RV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Production Data WM8532
w
PD, Rev 4.2, June 2014
13
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a
LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on
word length, BCLK frequency and sample rate, there may be unused BCLK cycles before
each LRCLK transition.
Figure 6 Left Justified Audio Interface (assuming n-bit word length)
In I
2
S mode, the MSB is available on the second rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word
length, BCLK frequency and sample rate, there may be unused BCLK cycles between the
LSB of one sample and the MSB of the next.
Figure 7 I
2
S Justified Audio Interface (assuming n-bit word length)
DIGITAL AUDIO DATA SAMPLING RATES
The external master clock is applied directly to the MCLK input pin. In a system where there
are a number of possible sources for the reference clock, it is recommended that the clock
source with the lowest jitter be used for the master clock to optimise the performance of the
WM8532.
The WM8532 has a detection circuit that automatically determines the relationship between
the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system
clock periods. The MCLK must be synchronised with the LRCLK, although the device is
tolerant of phase variations or jitter on the MCLK.
The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to
192kHz.
WM8532 Production Data
w
PD, Rev 4.2, June 2014
14
Table 3 shows typical master clock frequencies and sampling rates supported by the
WM8532 DAC.
Sampling Rate
LRCLK
MASTER CLOCK FREQUENCY (MHz)
128fs 192fs 256fs 384fs 512fs 768fs 1152fs
8kHz Unavailable Unavailable 2.048 3.072 4.096 6.144 9.216
32kHz Unavailable Unavailable 8.192 12.288 16.384 24.576 36.864
44.1kHz Unavailable Unavailable 11.2896 16.9344 22.5792 33.8688 Unavailable
48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable
88.2kHz 11.2896 16.9344 22.5792 33.8688 Unavailable Unavailable Unavailable
96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable Unavailable
176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable Unavailable
192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable
Table 3 MCLK Frequencies and Audio Sample Rates
HARDWARE CONTROL INTERFACE
The device is configured according to logic levels applied to the hardware control pins as
described in Table 4.
PIN NAME PIN
NUMBER
DESCRIPTION
MUTE¯¯¯¯¯ 19 Mute Control
0 = Mute
1 = Normal operation
AMPLSEL 20 Line Out Amplitude Level
1 = 2V
RMS
0 = 1V
RMS
DEEMPH 21 Audio Interface Mode
1 = De-emphasis filter active
0 = De-emphasis filter inactive
AIFMODE 22 Audio Interface Mode
1 = 24-bit LJ
0 = 24-bit I
2
S
Table 4 Hardware Control Pin Configuration
MUTE
The MUTE¯¯¯¯¯ pin controls the DAC mute to both left and right channels. If data is passing
through the device when the mute is asserted, a softmute is applied to ramp the signal down
in 944 samples. If no data is applied when the MUTE¯¯¯¯¯ pin is pulled low, then the mute will be
applied in one step after 4 samples. When the mute is de-asserted the signal returns to full
scale in one step.
AMPLSEL
The analogue line out full-scale amplitude can be selected to 1V
RMS
or 2V
RMS
. When 2V
RMS
is selected,
the full-scale output voltage at the LINEVOUTL/R pins is approximately 2V
RMS
. When 1V
RMS
is
selected, the full-scale output voltage at the LINEVOUTL/R pins is approximately 1V
RMS
. See the
Electrical Characteristics table for the full specifications of the full-scale output voltage.
Production Data WM8532
w
PD, Rev 4.2, June 2014
15
DE-EMPHASIS
A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is
44.1kHz. Operation at 48kHz and 32kHz is also possible, but with an increase in the error
from the ideal response. Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz
and 48kHz can be seen in Figure 10 to Figure 15.
POWER UP AND DOWN CONTROL
The MCLK, BCLK and MUTE¯¯¯¯¯ pins are monitored to control how the device powers up or down, and
this is summarised in Figure 8 below.
Figure 8 Hardware Power Sequence Diagram
Off to Enable
To power up the device to enabled, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 1.
Off to Standby
To power up the device to standby, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 0. Once the
device is in standby mode, BCLK can be disabled and the device will remain in standby
mode.
Standby to Enable
To transition from the standby state to the enabled state, set the MUTE¯¯¯¯¯ pin to logic 1 and start BCLK.
Enable to Standby
To power down to a standby state leaving the charge pump running, either set the MUTE¯¯¯¯¯ pin to logic
0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute
and power down quietly in either case.
Enable to Off
To power down the device completely, stop MCLK at any time. It is recommended that the device is
placed into standby mode as described above before stopping MCLK to allow a quiet shutdown.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

WM8532CGEFL/RV

Mfr. #:
Buy WM8532CGEFL/RV
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC, 2Vrms
Lifecycle:
New from this manufacturer.
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