1
®
FN7174.3
EL4584
Horizontal Genlock, 4F
SC
The EL4584 is a PLL (Phase Lock Loop) sub system,
designed for video applications but also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS compatible Pixel Clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 Sync Separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing, such as VTR head switching. The Lock detector
output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards, by external
selection of three control pins. These four ratios have been
selected for common video applications including 4F
SC
,
3F
SC
, 13.5MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
8F
SC
, 6F
SC
, 27MHz (CCIR 601 format) etc. use the
EL4585, which includes an additional divide-by-two stage.
For applications where these frequencies are inappropriate
or for general purpose PLL applications, the internal divider
can be bypassed and an external divider chain used.
Features
• 36MHz, general purpose PLL
•4F
SC
based timing (use the EL4585 for 8F
SC
)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
• Pb-Free available (RoHS compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture-in-Picture) timing generator
• Text or graphics overlay timing
Demo Board
A demo PCB is available for this product.
TABLE 1. FREQUENCIES AND DIVISORS
FUNCTION
3F
SC
(Note 1)
CCIR 601
(Note 2)
SQUARE
(Note 3) 4F
SC
Divisor 851 864 944 1135
PAL F
OSC
(MHz) 13.301 13.5 14.75 17.734
Divisor 682 858 780 910
NTSC F
OSC
(MHz) 10.738 13.5 12.273 14.318
NOTES:
1. 3F
SC
numbers do not yield integer divisors.
2. CCIR 601 Divisors yield 720 pixels in the portion of each line for
NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL in the active portion.
Ordering Information
PART NUMBER
PART
MARKING PACKAGE
PKG.
DWG. #
EL4584CN EL4584CN 16 Ld PDIP MDP0031
EL4584CS* EL4584CS 16 Ld SOIC MDP0027
EL4584CSZ*
(Note)
EL4584CSZ 16 Ld SOIC
(Pb-free)
MDP0027
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
**For 6F
SC
and 8F
SC
clock frequencies, see EL4585 datasheet.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet May 9, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Copyright Intersil Americas Inc. 2003-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
