4
FN7174.3
May 9, 2008
Pin Descriptions
PIN NUMBER PIN NAME FUNCTION
1, 2, 16 PROG B,
PROG C, PROG A
Digital inputs to select ÷ N value for internal counter. See Table 2 for values.
3 OSC/VCO OUT Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4 VDD (A) Analog positive supply for oscillator, PLL circuits.
5 OSC/VCO IN Input from external VCO.
6 VSS (A) Analog ground for oscillator, PLL circuits.
7 CHARGE PUMP
OUT
Connect to loop filter. If the H
SYNC
phase is leading or H
SYNC
frequency > CLK ÷ N, current is pumped
into the filter capacitor to increase VCO frequency. If H
SYNC
phase is lagging or frequency < CLK ÷ N,
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
8 DIV SELECT Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷ N.
9 COAST Tri-state logic input. Low (<1/3*V
CC
) = normal mode, Hi Z (or 1/3 to 2/3*V
CC
) = fast lock mode,
High (>2/3*V
CC
) = coast mode.
10 HSYNC IN Horizontal sync pulse (CMOS level) input.
11 VDD (D) Positive supply for digital, I/O circuits.
12 LOCK DETECT Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
13 EXT DIVIDER External Divide input when DIV SEL is low, internal ÷N output when DIV SEL is high.
14 VSS (D) Ground for digital, I/O circuits.
15 CLK OUT Buffered output of the VCO.
TABLE 2. VCO DIVISORS
PROG A (PIN 16) PROG B (PIN 1) PROG C (PIN 2) DIV VALUE (N)
000851
001864
010944
0111135
100682
101858
110780
111910
EL4584
5
FN7174.3
May 9, 2008
Timing Diagrams
FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0)
FIGURE 2. OUT OF LOCK CONDITION
FIGURE 3. TEST CIRCUIT 1
FALLING EDGE OF H
SYNC
+
200ns LOCKS TO RISING EDGE
OF EXT DIV SIGNAL.
200
Θ
E
= (tΘ/t
H
) × 360°
t
H
= H
SYNC
PERIOD
tΘ = PHASE ERROR PERIOD
200
EL4584
6
FN7174.3
May 9, 2008
Typical Performance Curves
FIGURE 4. I
DD
vs F
OSC
FIGURE 5. EL4584 OSC GAIN @ 20MHz vs TEMPERATURE
FIGURE 6. TYPICAL VARACTOR FIGURE 7. OSC GAIN vs F
OSC
FIGURE 8. CHARGE PUMP DUTY CYCLE vs θ
E
FIGURE 9. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
85
1.23W
0.91W
PDIP16
θ
JA
= +81°C/W
SO16 (0.150
”)
θ
JA
= +110°C/W
EL4584

EL4584CSZ-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Phase Locked Loops - PLL EL4584CSZ H-SYNC GEN LOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet