ADuM5230 Data Sheet
Rev. C | Page 10 of 15
APPLICATIONS INFORMATION
THEORY OF OPERATION
The dc-to-dc converter section of the ADuM5230 works on
principles that are common to most modern power supply
designs. It is implemented as an open-loop PWM controller,
which sets the power level being transferred to the secondary.
V
DD1
power is supplied to an oscillating circuit that switches
current into a chip-scale air core transformer. On the secondary
side, power is rectified to a dc voltage. The voltage is then
clamped to approximately 18 V and provided to the secondary
side V
OA
data channel and to the V
ISO
pin for external use. The
output voltage is unregulated and varies with load.
The PWM duty cycle is set by internal bias elements, but can
be controlled externally through the V
ADJ
pin with an external
resistor network. This feature allows the user to boost the
available power at the secondary, or reduce excess power if it is
not required for the application (see the Power Consumption
section).
Undervoltage lockouts are provided on the V
DD1
, V
DDB
, and V
ISO
supply lines to interlock the data channels from low supply
voltages.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM5230 digital isolator with a 150 mW isoPower®
integrated dc-to-dc converter requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins (see Figure 15).
The power supply section of the ADuM5230 uses a very high
oscillator frequency to pass power efficiently through its chip
scale transformers. In addition, the normal operation of the
data section of the iCoupler® introduces switching transients
on the power supply pins. Bypass capacitors are required for
several operating frequencies. Noise suppression requires a low
inductance high frequency capacitor; ripple suppression and
proper regulation require a large value capacitor. These are
most conveniently connected between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 14 for V
ISO
. To suppress noise and
reduce ripple, a parallel combination of at least two capacitors
is required. The recommended capacitor values are 0.1 μF and
10 μF. It is strongly recommended that a very low inductance
ceramic or equivalent capacitor be used for the smaller value.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypassing
with noise suppression and stiffening capacitors is recommended
between Pin 1 and Pin 2, a bypass capacitor is recommended
between Pin 7 and Pin 8. Bypassing with noise suppression and
stiffening capacitors is recommended between Pin 14 and Pin 15.
See the AN-0971 Application Note for board layout guidelines
and reduction of radiated emissions.
GND
1
V
DD1
V
ADJ
GND
1
V
OA
V
ISO
GND
ISO
DNC
V
IA
DNC
V
IB
GND
B
V
DD1
V
DDB
GND
1
V
OB
07080-022
DNC = DO NOT CONNECT
ADuM5230
TOP VIEW
(Not to Scale)
Figure 15. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this may
cause voltage differentials between pins exceeding the absolute
maximum ratings specified in Table 6, leading to latch-up
and/or permanent damage.
The ADuM5230 is a power device that dissipates about 1 W of
power when fully loaded and run at maximum speed. Because it
is not possible to apply a heat sink to an isolation device, the device
primarily depends on heat dissipation into the PCB through the
GND pins. If the device is used at high ambient temperatures,
care should be taken to provide a thermal path from the GND
pins to the PCB ground plane. The board layout in Figure 15
shows enlarged pads for Pin 1 and Pin 8. Implement multiple
vias from the pad to the ground plane, which significantly
reduce the temperatures inside the chip. The dimensions of the
expanded pads are left to the discretion of the designer and the
available board space.
THERMAL ANALYSIS
The ADuM5230 part consists of several internal die attached to
three lead frames, each with a die attach paddle. For the purposes
of thermal analysis, the device is treated as a thermal unit with
the highest junction temperature reflected in the θ
JA
parameter
shown in Table 2. The value of θ
JA
is based on measurements
taken with the part mounted on a JEDEC standard four-layer
board with fine width traces and still air. Under normal operating
conditions, the ADuM5230 operates at full load across the full
temperature range without derating the output current. However,
following the recommendations in the Printed Circuit Board
(PCB) Layout section decreases the thermal resistance to the
PCB, allowing increased thermal margin in high ambient
temperatures.
Under output short-circuit conditions, as shown in Figure 12,
the package power dissipation is within safe operating limits;
however, if the load is in the 100 Ω range, power dissipation is
high enough to cause thermal damage when the ambient
temperature is above 80°C. Care should be taken to avoid
excessive nonshort loads if the part is to be operated at high
temperatures.
