LTC3827-1
22
38271fe
APPLICATIONS INFORMATION
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has ad-
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20µF to 40µF of capacitance having a maximum of 20m
to 50m of ESR. The LTC3827-1 2-phase architecture
typically halves this input capacitance requirement over
competing solutions. Other losses including Schottky con-
duction losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ΔI
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recov-
ery time V
OUT
can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values.
The availability of the I
TH
pin not only
allows optimization of control loop behavior but also pro-
vides a DC coupled and AC fi ltered closed-loop response
test point. The DC step, rise time and settling at this test
point truly refl ects the closed-loop response
. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in Figure 13 circuit will provide
an adequate starting point for most applications.
The I
TH
series R
C
-C
C
lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
TH
pin signal which is in
the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R
C
and the bandwidth of the loop
will be increased by decreasing C
C
. If R
C
is increased by
the same factor that C
C
is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
LTC3827-1
23
38271fe
APPLICATIONS INFORMATION
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume V
IN
=
12V(nominal), V
IN
= 22V(max), V
OUT
= 1.8V, I
MAX
= 5A,
and f = 250kHz.
The inductance value is chosen fi rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
I
L
=
V
OUT
(f)(L)
1–
V
OUT
V
IN
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will
be the maximum DC value plus one half the ripple cur-
rent, or 5.84A, for the 3.3µH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 180ns is not violated. The minimum on-time occurs at
maximum V
IN
:
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specifi cation with some
accommodation for tolerances:
R
SENSE
80mV
5.84A
0.012
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
DS(ON)
= 0.035/0.022, C
MILLER
=
215pF. At
maximum input voltage with T(estimated) = 50°C:
P
MAIN
=
1.8V
22V
5
()
2
1+ (0.005)(50°C–25°C)
[]
0.035
()
+ 22V
()
2
5A
2
4
()
215pF
()
1
5–
2.3
+
1
2.3
300kHz
()
= 332mW
A short-circuit to ground will result in a folded back cur-
rent of:
I
SC
=
25mV
0.01
1
2
120ns(22V)
3.3μH
= 2.1A
with a typical value of R
DS(ON)
and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
P
SYNC
=
22V 1.8V
22V
2.1A
()
2
1.125
()
0.022
()
= 100mW
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02 for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(ΔI
L
) = 0.02(1.67A) = 33mV
P–P
LTC3827-1
24
38271fe
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connec-
tion at C
IN
? Do not attempt to split the input decoupling
for the two channels as it can cause a large resonant
loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
INTVCC
must return to the combined C
OUT
(–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3827 V
FB
pins’ resistive dividers connect to
the (+) terminals of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
Figure 11. LTC3827-1 Recommended Printed Circuit Layout Diagram
C
B2
C
B1
R
PU
PGOOD1
V
PULL-UP
(<8.5V)
C
INTVCC
+
C
IN
D1
1µF
CERAMIC
M1 M2
M3
M4
D2
+
C
VIN
V
IN
R
IN
I
TH1
V
FB1
SENSE1
+
SENSE1
PLLLPF
PLLIN/MODE
SGND
RUN1
RUN2
SENSE2
SENSE2
+
V
FB2
I
TH2
TRACK/SS2
TRACK/SS1
PGOOD1
TG1
SW1
BOOST1
BG1
V
IN
PGND
EXTV
CC
INTV
CC
BG2
BOOST2
SW2
TG2
LTC3827-1
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
38271 F11
+
C
OUT2
+
R
SENSE
R
SENSE
f
IN
F
CERAMIC

LTC3827EG-1#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators L IQ, 2x, 2-PhSync Buck Cntr
Lifecycle:
New from this manufacturer.
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